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Enable low power design with FPGAs

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re: Enable low power design with FPGAs
alalonso   11/6/2009 8:59:17 PM
When it comes to power, not all SRAM based FPGAs are created equal. New generation of these devices built on 65 nm technology and designed for portable applications have standby power in the single digit uA range and total power in the single digit mA range. Any power dissipation comparison needs to be viewed in terms of comparable parameters including logic resources, clock rates, temp, etc. Simply Stating SRAM based FPGAs can draw up to 1000x more static power than FLASH based FPGAs is irrelevant absent specifics of an exhaustive comparison of available solutions.

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re: Enable low power design with FPGAs
Byron196   11/5/2009 3:51:23 PM
Wendy, I believe I understand the intent of your statement: Taking time to design and debug an ASIC could lead to missing ever shrinking market windows or drive development costs very high that making a profit is impossible. However, the word "so" could have been included " so that making a profit is impossible". Overall I learned from your article.

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