Breaking News
Design How-To

Enable low power design with FPGAs

NO RATINGS
Page 1 / 3 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
alalonso
User Rank
Rookie
re: Enable low power design with FPGAs
alalonso   11/6/2009 8:59:17 PM
NO RATINGS
When it comes to power, not all SRAM based FPGAs are created equal. New generation of these devices built on 65 nm technology and designed for portable applications have standby power in the single digit uA range and total power in the single digit mA range. Any power dissipation comparison needs to be viewed in terms of comparable parameters including logic resources, clock rates, temp, etc. Simply Stating SRAM based FPGAs can draw up to 1000x more static power than FLASH based FPGAs is irrelevant absent specifics of an exhaustive comparison of available solutions.

Byron196
User Rank
Rookie
re: Enable low power design with FPGAs
Byron196   11/5/2009 3:51:23 PM
NO RATINGS
Wendy, I believe I understand the intent of your statement: Taking time to design and debug an ASIC could lead to missing ever shrinking market windows or drive development costs very high that making a profit is impossible. However, the word "so" could have been included " so that making a profit is impossible". Overall I learned from your article.

Radio
NEXT UPCOMING BROADCAST
How to Cope with a Burpy Comet
October 17, 2pm EDT Friday
EE Times Editorial Director Karen Field interviews Andrea Accomazzo, Flight Director for the Rosetta Spacecraft.
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll