The ever-changing safety regulations for using and designing electronic
equipment make implementing galvanic isolators into almost any data
acquisition and data transmission system necessary. One method of
isolating a control system's low-voltage circuitry from the potentially
dangerous high-voltages of the sensor and actuator sections in the
field is by using digital isolators.
To ease the design of isolated systems, this article describes the
basic functionality of a capacitive, digital isolator, explains its
placement within the signal path, and provides important
recommendations for a successful circuit board design.
Figure 1 shows the simplified block diagram of a
capacitive, digital isolator comprising a high-speed and a low-speed
signal path. The high-speed path (blue) transfers signals from higher
than 100 kbps to 150 Mbps, while the low-speed path (orange) reaches
from 100 kbps down to dc.
Figure 1. Simplified block diagram of a capacitive, digital
(Click on image to enlarge)
A high-speed signal processed in the blue path is differentiated into
fast transients by the capacitive isolation barrier. A subsequent
flip-flop (FF) then converts the transients into pulses identical in
shape and phase to the input signal. The internal watchdog timer (WD)
checks for the regular occurrence of high-speed signal edges. In the
case of a low-frequency input signal, the duration between consecutive
signal edges increases beyond the watchdog timing window. This forces
the watchdog to change the output switch position from the high-speed
path (position 1) to the low-speed path (position 2).
The low-speed path possesses a few more functional elements than the
high-speed path. Because low-frequency input signals require the
isolation barrier to assume prohibitively large capacitance, the input
signal is used to pulse-width modulate (PWM) the carrier frequency of
an internal oscillator (OSC). This creates a sufficiently high
frequency, capable of passing the capacitive barrier. Since the input
is modulated, a low-pass filter (LPF) is necessary to remove the
high-frequency carrier from the actual data before passing it on to the
Placement within the Signal Chain
Digital isolators come in the form of single-, dual-, triple- and
quad-channel devices for unidirectional and bidirectional operation.
All share these commonalities:
- do not conform to any specific interface standard
- use 3V/5V logic switching technology
- designed to galvanically isolate digital, single-ended (SE)
data lines only
While the last point appears to present a design limitation, Figure 2
shows how to isolate a wide variety of interfaces including low-volt
SPI, high-volt RS232, differential USB, and differential CAN/RS485.
All interfaces, however, have in common that the digital isolator must
be placed within in the single-ended, 3V/5V section of the isolated
Figure 2. Digital Isolators must be placed within the
single-ended section of an isolated interface
(Click on image to enlarge)
Because digital isolators have rise and fall times in the 1 to 2 ns
range, they are prone to signal reflections in the case of long signal
traces, whose characteristic impedance do not match the source
impedance of the isolator output. It is, therefore, recommended to
place an isolator in close vicinity to its corresponding data sinks and
sources such as controllers, drivers, receivers and transceivers. In
design where this is not possible, controlled impedance transmission
lines must be applied.