With the rise in design complexity and corresponding verification, many ASIC design teams are using FPGAs for prototyping and emulation. These hardware-based verification methods overcome performance shortcomings associated with software-based simulation, thereby allowing a greater number of test scenarios to be verified. However, with these advantages come several major issues that must be addressed when moving from software-based to hardware-assisted verification. Among these issues is the challenge to understand the internal behavior of the design prototype when the system does not perform as expected. FPGA prototyping and emulation can only be adopted if they provide sufficient visibility for efficient debugging. Furthermore, the visibility must be achieved with little overhead otherwise the benefit of performance gains will be erased by lengthened run times.
Inherent in silicon is the extremely limited signal access and visibility into the device. As a result, finding and analyzing the problems in FPGAs is dreadfully tedious and time consuming. Many approaches for improving FPGA debug focus on increasing visibility, such as multiplexing internal signals to output pins. However, these methods utilize significant resources to gain even the smallest insight into the silicon. Alternate methods – such as internal logic analyzers (ILAs) – are structured, but are more suitable for understanding the values of a few architectural registers rather than combinational logic values. These and other related methods often require a "trial and error" approach since the engineer may not initially know what part of the design needs to be examined. Each iteration is time-consuming because of the time it takes to insert observation points and recompile the design into the FPGA. And once the relevant signal values are accessed, the next step is analysis. Because extracting the data and analyzing it are so tightly integrated, the arduous task of debugging the FPGA has become a major bottleneck in adopting prototyping and emulation techniques for verification.
In order to reduce the time-consuming process of debugging the FPGAs, upfront planning is necessary. Appropriately configuring the system and performing the following steps will increase the internal signal value visibility for faster debug:
- Implement an on-chip signal access mechanism (often referred to as design-for-debug or DFD logic) in the FPGA to enhance the ability to retrieve crucial signal data through improved design observability.
- Retrieve the data while the FPGA is operating in-situ.
- Process the retrieved data
- Expand the signal data to enable appropriate deep analysis techniques.
- Correlate the gate-level signal data to the register transfer level (RTL) so the designer understands the intended behavior.
The system must be properly connected to allow signal data flow from the internal nodes of the FPGA to the visibility enhancement engines. The system consists of the instrumented FPGA, pod and cable, which attach the printed circuit board (PCB) to a computer. Running on the computer is an application that controls the on-chip signal access mechanism. The application is capable of retrieving internal signal data, then writing it out to a file. For full visibility of all signal values at the RTL, the file must be further processed with visibility enhancement techniques (Fig 1).
To provide guidance for the DFD and maximize usefulness of the extracted signal data, Novas Software provides "visibility enhancement" technology with its new Siloti SilVE product. Visibility enhancement technology includes 1) design analysis to determine the optimal signal probe points, 2) data expansion to compute combinational signal values that were not extracted, and 3) abstraction correlation to present gate-level signal values at the RTL.
Implementing design for debug – optimal signal selection
To facilitate acquiring value data from internal signals, DFD logic must be inserted into the functional blocks in the design prior to compilation. Fortunately for designers, commercial ILA solutions for FPGAs are widely available and effectively serve as DFD IP. The ILAs usually consist of mechanisms to access internal signals and optional event triggering when the FPGA is operationally executing. When selecting an ILA solution, consider the features listed in (Table 1.
The ILAs provide a way to bring out a limited set of internal signal values for observation, but leave it to the user to determine the best points to observe. To determine the optimal probe or observe points, proceed as follows:
- Determine the module or level of hierarchy for observation.
- List any signals that should always be probed for observation.
- Provide this information to the Siloti SilVE product to analyze and determine the essential set of additional signals that must also be observed.
- Compute the percent of combinational logic that will be observable using the Siloti SilVE product.
- Pass the list of essential signals to the ILA insertion process.