Clock Circuitry: Special I/O blocks with special high drive clock buffers, known as clock drivers, are distributed around the chip. These buffers connect to clock input pads and drive the clock signals onto the global clock lines described above. These clock lines are designed for low skew times and fast propagation times. Note that synchronous design is a must with FPGAs, since absolute skew and delay cannot be guaranteed anywhere but on the global clock lines.
SRAM vs. Antifuse vs. Flash
There are three competing technologies for programming FPGAs. SRAM programming involves a small static RAM bit for each programming element. Writing the bit with a zero turns off a switch, while writing with a one turns on a switch. Another method involves an antifuse that consists of a microscopic structure that, unlike a regular fuse, normally makes no connection. A large amount of current during programming of the device causes the two sides of the antifuse to connect. A third and relatively new method uses flash EPROM bits for each programming element.
The advantages of SRAM-based FPGAs – the most common programming technology by far – is that they use a standard fabrication process that chip fabrication plants are always optimizing for better performance. Since the SRAMs are reprogrammable, the FPGAs can be reprogrammed any number of times, even while they are in the system, just like writing to a normal SRAM. SRAM devices can easily use the internal SRAMs as small memories in the design.
The disadvantages of SRAM-based FPGAs are that they are volatile, which means a power glitch could potentially corrupt the contents of the device. SRAM devices have large routing delays and are slower than other technologies, in theory, but continually improving SRAM technology has effectively eliminated this disadvantage. SRAM FPGAs can consume more power and are less secure than other technologies because they must be reprogrammed upon power-up and the programming bitstream can be observed going into the device. Custom SRAM FPGAs with built-in keys that unencrypt incoming program bit streams can be purchased from vendors, but this reduces the low cost and fast lead time advantage of the FPGA. Bit errors are also more likely with SRAM FPGAs than with the other devices. The market has decided that the advantages of SRAM FPGAs outweigh the disadvantages as they are by far the dominant FPGA technology.
The advantages of antifuse FPGAs are that they are non-volatile and the delays due to routing are very small, so they tend to be faster. Antifuse FPGAs tend to require lower power and they are better for keeping your design information out of the hands of competitors because they do not require an external device to program them upon power-up as SRAM devices do. The disadvantages are that they require a complex fabrication process, they require an external programmer to program them, and once they are programmed, they cannot be changed. The complex, nonstandard fabrication process has turned out to be a key disadvantage as antifuse FPGAs have lower yields and the technology has improved more slowly than SRAM FPGAs.
Flash FPGAs seem to combine the best of both of the other methods. They are nonvolatile like antifuse FPGAs, yet reprogrammable like SRAM FPGAs. They use a standard fabrication process like SRAM FPGAs and they are lower power and secure like antifuse FPGAs. They are also relatively fast. Currently, one vendor supports flash FPGAs and another vendor has a hybrid flash/SRAM FPGA. They are not catching on as fast as I expected, though that could change in the future.
Example FPGA families
Examples of SRAM FPGA families include the following:
- Altera Stratix II and Cyclone II families
- Atmel AT6000 and AT40K families
- Lattice LatticeEC and LatticeECP families
- Xilinx Spartan-3 and Virtex-4 families
Examples of antifuse FPGA families include the following:
- Actel SX and Axcelerator families
- Quicklogic Eclipse II family
Examples of flash FPGA families include the following:
Examples of hybrid flash/SRAM FPGA families include the following:
Cores: When I talk about a "core" I am simply referring to a large self-contained function. There are two basic types of cores. The soft core, known as an IP core, is a function that is described by its logic function rather than by any physical implementation. Soft cores usually consist of hardware description language (HDL) code. Hard cores, on the other hand, consist of physical implementations of a function. With respect to FPGAs, these hard cores are known as embedded cores because they are physically embedded onto the chip die and surrounded by programmable logic.
Many FPGA vendors have begun offering cores. The density of programmable devices is increasing, enabling what is called a Programmable System on a Chip (PSOC). Whereas programmable devices were initially developed to replace glue logic, entire systems can now be placed on a single programmable device. SOCs include of all kinds of complicated devices, like processors. In order to place these complex functions within a programmable device, there are three options: the first is to either (a) design the function yourself and place it in the programmable logic, (b) purchase the HDL code for the function and incorporate it into your HDL code, or (c) get the vendor to include the function as a cell embedded in the programmable device. The second option is the IP core or soft core, while the third option is the embedded core or hard core.
IP Cores: IP cores are often sold by third party vendors that specialize in creating these functions. Recently, FPGA vendors have begun offering their own soft cores. IP cores reduce the time and manpower requirements for the FPGA designer. IP cores have already been designed, characterized, and verified. Also, IP cores can often be modifiable, meaning that you can add or subtract functionality to suit your needs. They are also portable from one vendor to another.
But IP cores may also be expensive. Electrical characteristics such as timing or power consumption for IP cores can be optimized to a limited degree, but the actual characteristics depend on its use in a particular device and also depend on the logic to which it is connected. IP cores purchased from a third party may not be optimized for your particular FPGA vendor's technology. You may not be able to meet your speed or power requirements, especially after you have placed and routed it.