As the industry transitions from traditional, bus-based shared I/O schemes with system synchronous clocking (such as PCI), point-to-point system interconnects that use serial I/O technologies are fast becoming the norm. While PCI has been the most widely used bus standard in the PC, server and embedded market for the past decade, PCI Express – with its wide appeal across industry segments – is widely seen as the future of PCI. In fact, it is estimated that PCI Express will replace 80% of all existing PCI ports by the end of 2007 (Fig 1).
1. Illustrated here is the forecast for PCI Express port.
PCI Express is a high-speed serial I/O technology that employs a clock data recovery (CDR) technique. Instead of using a system synchronous or source synchronous clock, the clock is embedded into the data stream and recovered at the receiver. In general, serial I/Os reduce pin count which in turn reduces the number of traces on the PC Board (PCB), the size of the PCB, and the number of layers, and also simplifies the lay-out and design of PCBs (Fig 2). Fewer pins also translate to reduced noise and electromagnetic interference (EMI). CDR eliminates the clock-to-data skew problem prevalent in wide parallel busses, making interconnect implementation easier. When these advantages - smaller and thinner PCBs, easier lay-out, smaller enclosures, and reduced cooling requirements - combine together, a significant cost savings can be realized.
2. Using PCI Express (bottom) can reduce system development cost compared to traditional interconnect (top).
Standard products based on PCI Express, such as chipsets, graphics processors, and switches that support the standard PCI Express architecture are now available in mass quantity. PCs and servers that use these products have started volume production. In fact, a PC with three PCI Express slots – x1, x4 and x16 – can be purchased for under $1,000 (US dollars). In addition, FPGA-based PCI Express implementations, which marry FPGAs such as the Xilinx Spartan-3 or Virtex-4 with IP cores, are also available. While standard chip manufacturers and early adopters previously used these implementations as prototyping vehicles, today they are key to making any technology successful in the embedded (e.g. communications, storage, industrial, or medical) market. This trend matches well with the projected mass scale adoption of PCI Express into the embedded space around 2006 (Fig 3).
3. Shown here is the adoption roadmap for PCI Express.
While the adoption of PCI Express in the personal computer and server space is a given, its adoption in the embedded space will be driven by programmable logic. The majority of embedded processors today use a local bus that is somewhat different than PCI. Most PCI Express Application Specific Standard Products (ASSPs) support PCI as the backend bus of choice. This makes an FPGA-based PCI Express solution ideal for the embedded market. The FPGA's flexibility and low risk enable embedded designers to implement products that can be differentiated from the competition. FPGAs also reduce the supply chain cost, translating to significantly lower system cost. More importantly, designers are able to realize optimized designs with faster time-to-market, which in turn means increased profits.
Designing embedded systems
In general, embedded designs do not fully rely on a standard architecture or specification. Embedded designers typically add their own "secret sauce" to existing standards, such as PCI Express, so as to create a solution that can be differentiated from the competition. To that end, standard products such as PCI Express switches and root complexes will be used wherever possible to reduce costs, while key functionality like protocol bridging and traffic management will be implemented in custom logic (e.g. an ASIC or FPGA). Sometimes the design requires the ability to do protocol conversion such as from PCI Express to an MPEG stream. If the volume is high enough an ASSP can provide this functionality, although in most instances that will not be the case. The availability of PCI Express in an FPGA gives designers the ability to create a design that exactly matches their requirements, rather than shoehorning an existing product. A designer could easily create a bridge using an FPGA from a MIPS processor, for example, that supports HyperTransport to a PCI Express switch. This bridge can then talk to cheap PCI Express peripherals, as opposed to more expensive HyperTransport peripherals.
Another requirement for the designer is to reduce the total system cost as a means of protecting profit. There are several factors that add to the total cost of the system. These include the cost in managing the supply chain such as inventory cost, product qualification cost, and the cost associated with design and manufacturing; mask cost; silicon respins; and assembly. There is also the indirect cost associated with time-to-market and time-in-market. The quicker a product gets to market, and the longer it stays in the market, the greater the impact on a company's top and bottom lines.
While re-programmability, fastest time-to-market and longest time-in-market are the biggest value propositions of the FPGA, reducing total system cost is another big advantage that is sometimes overlooked. One of the major advantages of using PCI Express components is their low cost compared to PCI. FPGA-based PCI Express implementations can therefore drive the usage of cheap PCI Express standard products into the embedded space. This will allow customers to reduce costs while providing the ability to match the peaks and valleys of market demand.