Regardless of the amount of time and energy FPGA designers invest attempting to create "right-first-time" designs, the functional complexities, performance requirements, and high gate counts of large complex designs frequently require changes to correct logic problems or to provide further optimization. Compared with a traditional flow, an "incremental" design flow for design/synthesis and place-and-route physical implementation is highly desirable with regard to repairing or optimizing specific parts of the design without disturbing other portions that have met their design requirements.
When a top-down design approach is difficult due to system memory limitations or extensive run times, an incremental design flow also enables designers to process large designs. Other design strategies involve freezing sections of a completed design while other parts of the design are continuing development independently.
Traditional design creation and physical implementation
The common flow for FPGA development is to:
- Create the design in HDL.
- Run pre-synthesis simulation.
- Set constraints.
- Synthesize the design.
- Run post-synthesis simulation.
- Run place and route.
- Analyze the design's timing performance.
If functional and timing performance requirements are met, a programming file is generated and the device is programmed. Using tools from Actel and its partners, the Libero IDE Platinum toolset is well equipped to successfully manage a "right-first-time" design. For performance improvements, the Actel SmartTime timing analysis and constraints management tool provides features for identifying and resolving critical paths within the design. Additionally, the Magma PALACE physical synthesis tool can generally improve the overall performance of Actel's Fusion Programmable System Chips and ProASIC3 devices by a significant margin.
But what if further optimization on segments of the design need to be managed after the initial layout? What if performance is still marginal, or some of the blocks still contain functional problems?
Incremental design flow overview
The design flow (Fig 1) closely resembles a traditional synthesis/physical implementation flow, with the addition of "compile points" after the initial synthesis project setup and compile. Compile points are parts of a design that act as relatively independent synthesis units: they have their own constraint files and are optimized individually. They are re-synthesized only as needed, based on an analysis of design dependencies and the nature of design changes. Compile points are locked, to ensure stability in incremental design and to permit hierarchical place and route with multiple output netlists (one for each compile point and one for the top level of the design). A "locked" compile point means that, during synthesis of its parent, it is not re-optimized, its hierarchical interface is unchanged, and no boundary optimizations are made. This implies that all instantiations of the same locked compile point have the same implementation and are treated identically during synthesis.
1. Incremental flow using Synplify Pro and Libero IDE.
(Click this image to view a larger, more detailed version)
Alternatively, design teams can work on individual compile points simultaneously and independently. Each compile point is treated as an individual block for incremental and individual mapping. Any number of compile points can be identified and nested into the design. Using compile points, design modifications can be managed without disturbing other parts of the design.
A "difference-based" incremental synthesis process keeps track of design changes and dependencies. Re-synthesis occurs only on those parts of the design that are directly affected by the incremental change. The process also ensures that the incremental changes made are identifiable in the netlist to the corresponding netlist import and compile function. Keeping the original place and route as golden as possible is ensured by running the updated netlist using an "Incremental Mode" and "Lock Existing Layout' option in a Layout Options menu. Updates and modifications will occur to only those parts of the layout that are directly related to the compile point changes made by the synthesis tool.
The Synplify Pro MultiPoint synthesis and the Actel Libero Integrated Design Environment (IDE) together provide an efficient incremental design flow methodology for managing true engineering change order (ECO) requirements. This combination allows modular changes to the original design, whereby only those parts of the design that need to change will change. This flow minimized the impact on previously proven segments of the design, thus saving time and resources.
For example, the MultiPoint synthesis solution allows you to establish a multiple of "compile points" that are preserved in Synplify Pro as future design or redesign areas. You may also partition a design into small synthesis blocks for modification while leaving the remainder untouched. For very large designs, MultiPoint allows designing and synthesizing in incremental blocks in order to avoid system memory or runtime issues.