The low-cost FPGA marketplace
Over the last several years, the popularity of low-cost Field Programmable Gate Arrays (FPGAs) has increased dramatically, to the point where low-cost FPGAs now represent approximately 25% of the overall market. However, the features these products provide (or do not provide) have limited the applications that can utilize low-cost FPGAs. The challenge for FPGA providers is to increase the feature set of these devices while continuing to deliver the attractive price points that have made these devices so popular.
This article examines the need for, and approaches to, providing enhanced low-cost FPGA capability in the areas of SERDES, DSP, high-speed source synchronous I/O, memory capacity and device configuration. The article concludes with a summary of the second generation EConomy Plus FPGAs from Lattice Semiconductor, and the approaches taken to address these five capabilities.
SERDES functionality: a new need in low-cost FPGAs
Once the domain of high-end communications equipment, SERDES technologies are becoming increasingly important for more cost-sensitive devices. The adoption of SERDES-based PCI Express in the PC is well underway, and the technology now is migrating to a variety of other equipment as a replacement for the original PCI interface, which is now over a decade old. In cost-sensitive edge and access equipment, including that targeted for rapidly emerging triple play (phone, video and data) applications, Gigabit Ethernet (GbE) and Serial Gigabit Media Independent Interface (SGMII) are becoming increasingly common interfaces between PHY devices and the remainder of the system.
In the wireless base station market, cost reduction is becoming increasingly important and likely will be enabled in part by the standardization that the serial Common Public Radio Interface (CPRI) and Open Base Station Standards Initiative (OBSAI) provide.
Despite the tremendous pent-up demand for SERDES in low-cost systems, until recently, only higher performance, higher cost FPGAs have provided SERDES capability. Generally, the SERDES in high performance FPGAs have focused on driving performance in a number of directions, such as link speed, number of channels, ultra low jitter, support for long Consecutive Identical Digits (CID, as found in SONET) and the capability to drive long backplanes. While appropriate for high end FPGAs, this focus on performance has resulted in cost and power characteristics that are inappropriate for low power applications.
DSP functionality in low-cost FPGAs
The applications of Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR). Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high performance, low-cost DSP solutions.
Designers often implement structured DSP functions that require significant computation resources within FPGAs. This approach allows the selection of a lower performance general purpose DSP processor, and results in lower overall system costs. Examples of structured functions that are commonly implemented within FPGAs include Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFTs) and mixers. Typical implementations of FIR and FFT functions are shown in Fig 1. These implementations share the characteristic of requiring multiplication followed by addition, subtraction or accumulation.
1. Typical implementations of FFT and FIR functions.
To date, three approaches have been taken when implementing DSP functions within low-cost FPGAs. The first approach adopted was to implement the DSP functions using the general purpose Look-Up Tables (LUTs) available within the device. While flexible, this method provides relatively low performance and consumes a significant quantity of the general purpose FPGA logic.
As a result, all current generation low-cost FPGAs take one of two enhanced approaches. The first approach is to implement multipliers as hard logic within the FPGA fabric. This reduces the general-purpose FPGA resources that are required to implement DSP functions. However, as previously noted, most typical DSP functions implemented within FPGAs require additional subtraction, addition or accumulation functions after the multiplier. These functions in themselves can consume significant FPGA resources and – with typical final data widths running upwards of 36-bits – they are often the performance bottleneck in the design. To address this challenge, the latest FPGAs utilize efficient hard logic to provide programmable addition, subtraction and accumulation after the multiplier. By providing DSP functionality in this manner, usage of general-purpose resources is minimized and high performance operation is achieved easily. Table 1 summarizes the three different approaches.
Table 1. Summary of different DSP approaches.
High-speed parallel interfaces for low-cost FPGAs
Designers of low-cost systems find it increasingly important to implement high performance parallel interfaces (often referred to as source synchronous interfaces) within low-cost FPGAs. Several system requirements typically drive this need. In some cases it is necessary to interface with DDR SDRAM memory, which is rapidly becoming the lowest cost, high capacity memory available to designers. In other instances it is necessary to support the high performance SPI4.2 communications standard that is common to many forms of communication equipment. In yet other instances it is driven by the need to interface to high performance Analog to Digital Converters (ADCs) or Digital to Analog Converters (DACs).
Implementation of high performance source synchronous interfaces typically poses four challenges to FPGA designers:
- The conversion of signals from Single Data Rate (SDR) to Double Data Rate (DDR), a process that results in significantly less margin than is available in the processing of the SDR data typically used within FPGAs.
- The adaptation of speed between high performance I/Os and the FPGA fabric. Again, this processing is done with significantly less margin than is typically available in FPGA designs.
- The alignment of the clock (sometimes referred to as DQS or Strobe) and data in order to correctly transmit or receive information. This requires the ability to insert precision delays in the clock path relative to the datapath.
- The transfer of data from the external clock domain to the system clock domain used within the FPGA. If this task is not approached correctly, a design may well experience problems in the field or during volume manufacture, even if the prototypes operated correctly in the lab.
Generally, hard logic to implement these four functions can be added to the FPGA design with minimum impact on die area and, therefore, device cost. Today all low-cost FPGAs provide some of these capabilities as hard logic in the I/O circuitry, with the most advanced providing all four functions as hard logic. FPGAs that provide all four functions deliver higher performance, lower general-purpose logic usage and faster design cycle time.