Algorithm-driven design is the norm rather than the exception for the modern system designer, often requiring them to incorporate higher performance integrated circuits (ICs). Unfortunately, the pressure to get products to market – coupled with restricted budgets – rules out application-specific integrated circuits (ASICs). As a result, more and more embedded system designers are turning to programmable logic devices and away from the ASIC approach. To date, the most popular programmable logic choice has been field programmable gate arrays (FPGAs) or digital signal processors (DSPs). Although these devices have enjoyed broad market acceptance, they aren't great at scaling to meet high-performance system requirements.
A new category of very high-performance programmable logic devices has been developed to address the un-met needs of system designers. The MathStar Field Programmable Object Array (FPOA) is an example of this category, offering field re-programmability, 1 GHz performance, a 400-object array, high-speed I/O, and a streamlined design process. The design methodology of an FPOA leverages the use of building blocks called "objects" rather than "gates" used in an FPGA. This object approach allows an FPOA to operate at 1 GHz, up to four times faster than an FPGA, while still offering all the benefits of a programmable logic device. The FPOA has been developed to provide deterministic timing so no timing closure is required. As opposed to an FPGA, a 1 GHz FPOA will always operate at 1 GHz. The result is a much higher performance solution than what is attainable in other reprogrammable solutions.
FPOA application performance in image processing
Because of its high-performance, the FPOA is useful in a wide range of applications, including those in the areas of machine vision, professional video, medical imaging and image processing. These applications are built around extremely fast building blocks, such as flat field error correction, Fast Fourier Transform (FFT), Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, Discrete Cosine Transform, 2D convolution filters, and even video codecs such as MPEG2, JPEG2000 and MPEG4/H.264. This article will cover three examples: flat field error correction, FFT and 2D convolution filter.
Flat Field Error Correction: Flat field correction is a very important algorithm in many industries, including professional video, security and surveillance and machine vision. It's used to adjust image sensor output data to ensure that errors and flaws in the optical sensor are not propagated to the rest of the system.
This correction process addresses three types of pixel-based non-uniformities: gain, dark current offset and defective pixels. In order to rectify these non-uniformities, a calibration and correction process must be performed. The calibration process determines the correction factors for pixel gain and offset, and generates a defective pixel map. The correction process takes these factors and calculates an appropriate value for non-uniform pixels.
As sensor resolutions grow to 4K × 4K and beyond, the computation requirements for flat field error correction go up exponentially. Using only 13 to 22 objects, the FPOA architecture is able to sustain performance rates of 500 megapixels per second in continuous flat field error correction. This is more than four times the performance of a large FPGA and supports over 60 frames per second for a 4K × 2K image sensor. Rates higher than 1 gigapixel per second are achievable by implementing several flat field error correction blocks in parallel within a single FPOA.
Fast Fourier Transform: The FFT is an ingenious algorithm that is used for applications that require a discrete signal to be converted from the time domain to the frequency domain. The performance metrics of an FFT include the number of bits used to represent each sample, the number of samples, or points, in the FFT representation, and the rate at which the FFT can handle new inputs, also known as the sample rate.
The FPOA architecture is ideal for FFTs with sample rates at 1 Giga sample per second. This performance level is up to four times what a large FPGA can accomplish. Table 1 shows performance benchmarks for various FFTs implemented on a 400 object FPOA.
Table 1. FFT performance when implemented on an FPOA.
2D Convolution Filter: Convolution kernels are a common and necessary component of image processing systems. The basic structure of the convolution kernel is used in spatial filtering, edge detection and other areas of image processing. The basic idea is to scan an entire image with a mask (also called the kernel), generating a weighted sum for each pixel. Depending on this weighted sum and the contents of the kernel, specific information about the image can be determined. The 2D convolution algorithm consists of arithmetic operations on pixels and memory buffers for localized image storage. As shown in the flat field error correction example, the architecture of the FPOA is well suited to these types of pixel-based applications. The FPOA is able to achieve a much higher pixel processing rate than FPGA architectures. Table 2 shows the object usage for various performance levels of 2D convolution filters.
Table 2. 2D convolution filter performance and resource utilization estimates for FPOA.