There has been an increasing demand to add multiple Secure Digital (SD) devices in a single system. The problem, however, is that most host devices/processors, for example Intel PXA270, TI OMAP, or Qualcomm MSM processors, only provide a single SD interface. Fortunately, Complex Programmable Logic Devices, otherwise known as CPLDs, can be used to allow host devices to support any number of SD devices. This article details a scalable, auto-sensing bidirectional multiplexer-based design.
Creating an SD Multiplexer using CPLDs
Fig 1 shows a generalized CPLD usage model to incorporate any number of SD ports for a given host device that only has a single native SD interface. The CPLD is placed between the host controller and the SD devices. As such, the CPLD part performs a bidirectional multiplexing function, allowing the host to communicate with any selected SD Device. More importantly, this design has no directional control pins, which means that the CPLD automatically detects the direction of data flow.
1. Using CoolRunner-II CPLDs to provide additional SD ports.
This implementation is extremely flexible and scalable, meaning that the number of SD ports can be increased or decreased as desired. The design also supports any of the defined SD card modes – SPI, 1-bit, or 4-bit data modes.
While the primary purpose of using a CPLD device in this type of application is to provide additional SD ports to the host controller, secondary benefits include level translation and logic isolation between the host and the SD card. Fig 1 shows the case where the host is 1.8V, but the SD Devices are 3.3V. The industry's latest CPLDs provide negligible standby current and ultra low dynamic power consumption. Hence, incorporating a complex programmable logic device in your system will not significantly impact your power budget.
Compliance with the SDA Specification
The SDA (Secure Digital Association) specification states that one SD bus can only support one SD device. The clock pin can be shared, but the DAT[3:0] and CMD lines must be unique for every SD device (additional details are shown in Fig 2).
2. SD system bus topology.
This reference design is fully compliant with the SDA Specification. The following discussions will demonstrate how to satisfy the above requirements while supporting any number of SD devices using a controller with a single bus.
A block diagram showing typical use of this design for two SD devices sharing the same SD host interface can be seen in Fig 3. Conceptually, the design can be viewed and used as a bidirectional multiplexer. The host device controls the CPLD via the Select signals, thereby dictating which SD device to communicate with. Once an SD device has been selected, the logic in the CPLD device automatically detects the direction of data flow and allows data to stream accordingly (either from the host to the SD card or from the SD card to the host). A directional control pin is not required, thereby making this design easy to use.
3. Block-level diagram – a bidirectional multiplexer.
The host can access each SD device individually without affecting the state of the other when the multiplexer is switched accordingly. If neither the host nor the SD is driving data, the CPLD allows the system to be in the default high impedance with weak pull-up state. The primary purpose of this circuit is to provide additional SD capability to the host, but this circuit can also be used to provide level translation and/or logic isolation.
Fig 4 shows the actual logic circuit for a 1:2 bidirectional multiplexer design, which can be described using VHDL. In the initial condition or idle state, the Host and SD Cards should be high impedance with a weak pull-up. Hence, the circuit in Fig 4 is designed to tristate the CPLD's output buffers, thereby allowing the external pull-up resistors to take effect. Register A (A_REG) and Register B (B_REG) are both designed to be initialized to logic '0' upon power-up.
4. SD multiplexer circuit for two SD devices.
(Click this image to view a larger, more detailed version)
The SD Cards are selected via the Select inputs to the CPLD. When Select is logic '0', SD1 is chosen; when Select is logic '1', the SD2 device is chosen. For simplicity while describing this circuit, let's assume in the following discussion that the Host is only choosing to communicate with SD1.
The auto-directional control aspect of this design is implemented in the following manner – a transaction is initiated when either the host or SD1 drives Low. For example, if the host wants to send data to the SD1 device, the host would begin by driving the A side Low. Upon driving Low, the logic in the circuit detects the Low going edge and responds by enabling the B output buffer, but continues to keep the A output buffer disabled. Specifically, when A is driven Low, a rising edge is delivered to the clock input of A_REG. After clocking, the Q output from A_REG becomes logic '1' and therefore prevents B_REG from receiving a clocking event. In parallel with the A_REG clocking and triggering, gate B1 outputs a logic '1' when A goes Low. This enables the B output buffer and, ultimately, B will follow A and drive Low.
Conversely, when it is driven from Low to High, gate B1 outputs a Low and tristates the B output buffer. This forces B to go High via the external pull-up resistor. Once the A and B sides are both High, A_REG and B_REG are reset to 0. This process is repeated indefinitely. The reverse happens when SD1 attempts to drive data toward the host. Additionally, if the host wishes to communicate with the SD2 device, the Select inputs to the circuit are set to a logic '1' and the sequence of events are similar to the above.