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How to turn every FPGA LVDS pair into a complete SERDES solution

9/26/2007 06:00 PM EDT
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jamesrandall
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
jamesrandall   6/26/2012 7:04:18 AM
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ALL technology is cerainly exciting indeed. I can see a lot of promise with this new technology, and I am sure that maufacturers will start to pay more attention to it soon enough.

mwinnc
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
mwinnc   10/8/2007 2:35:06 PM
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Max - excellent refresher for some of us. a couple of notes: you only list two major FPGA suppliers, but there are three: Lattice has ECP2 on the low end; and SC on the high end. The key however, is the ECP2M which incorporates significant memory resources and up to (16) 3.125G SerDes at a Spartan/Cyclone cost point. This allows engineers to implement full function SerDes (full PCS layer) at minimal extra cost. And with (8) PLLs, clocking resources are not an issue.

Max The Magnificent
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
Max The Magnificent   9/27/2007 9:04:05 PM
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Good catch --- you are right -- I was thinking 3 1/8 and I just wrote 3.8 ... but I should have caught that when re-reading the little scamp because (a) I know it's 3.125 and (b) i'm an anal-retentitive and I usually re-perform the calculations "just to make sure" ... Thansk for the "heads up" -- cheers -- Max

EDW
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
EDW   9/27/2007 4:38:38 PM
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Also also, if you examine 8b/10b encoding (perhaps via spreadsheet) you will find that there are not enough unbiased (5 zeros and 5 ones) 10b characters (252 by my calculations) to cover the 8 bit input (256). So some biased 10b characters are pressed into service, and an output circuit is employed that enforces "neutral disparity" by inverting entire 10b characters when necessary. Of course, someone (legacy devices) decided negative disparity when idle was necessary, further mucking things up. It never ceases to amaze me how, on the occasion that engineers build something beautiful, others invariably come along and turn it into a Frankenstein.

EDW
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
EDW   9/27/2007 4:17:04 PM
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Also, jitter is only attenuated if it is above the pass band of the PLL, otherwise it is passed on (if the pass band is flat) or even amplified (if the pass band is peaky). Thus the concern over wander accumulation in any synchronous digital hierarchy.

EDW
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
EDW   9/27/2007 4:13:40 PM
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Nice article Max, thanks! Typo alert: "This means that ? for every 8 bits of data we wish to transmit or receive ? we actually end up using 10 bits. Thus, in the case of a 2.5 gigabits-per-second data rate, the corresponding link rate is actually 3.8 gigabits-per-second." For a 2.5 gbps data rate, the line rate is 2.5 * 10 / 8 = 3.125 gbps You probably meant 3 1/8 gbps.

LonM
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re: How to turn every FPGA LVDS pair into a complete SERDES solution
LonM   9/27/2007 3:24:42 PM
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this is similar to an idea that I had to transmit parallel data over widely seperated paths. Multiple slaves all used the same basic reference clock (which could be sent from the master, or shared from a third source). Each slave must have a PLL with a phase adjuster that must be register programmable (like Cyclone3). They transmit the clock back to the Master, and the master measures the phase skew between them. The master sends the phase adjust commands to each slave. The loop integrates down to bring all slave clocks into alignment at the master. The master can now latch the slave data together, or use a FIFO to cross the data into the Master's own clock domain. As long as the slave FPGA has an adjustable phase PLL, it can be done without additional hard logic.

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