Editor's Note: Generally speaking we (Programmable Logic DesignLine) are not in the business of publishing user guides for specific device families. But one of my favorite sayings (in addition to someone else exclaiming "My round, I think!") is the classic: "Rules are intended for the guidance of wise men and the blind obedience of fools."
The point is, where do you go to learn more about a specific family of FPGAs, for example? The vendor's data sheets are great if you are already an expert looking for a specific nugget of information, but more-often-than-not they are a pain in the rear end, telling you everything except the fact you're trying to tie down.
At the other end of the spectrum are the vendor's main User Guides, but these can number hundreds or thousands of pages and are presented in such excruciating detail as to bring even the strongest amongst us to our knees.
If only there were something in between . . . Which brings us to this article, which is a User-Guide Lite for the Xilinx Virtex-5 family of FPGAs.
In fact I think that this is an incredibly good idea. I would love to see the same treatment for all of the major FPGA and CPLD families from all of the vendors. My message is: "If you write them, they will come. . ." So, over the course of time, I hope to build a little "library" of these guides . . . watch this space!
What is the purpose of this paper?
This paper gives potential users an easy-to-grasp idea of the capabilities of the device functions of Xilinx Virtex-5 FPGAs. It describes the functionality of these devices in far more detail than in the data sheet, but avoids the minute implementation details covered in the various Virtex 5 FPGA User Guides.
Any designer contemplating designing with Virtex-5 FPGAs faces a dilemma: The first four pages of the data sheet give very concentrated information about the whole family, without describing the capabilities in enough detail. By comparison, the User Guides give all the details that the designer needs, but – at more than a thousand pages – it may require weeks of work to read and understand all of the details.
This paper describes the capabilities (what you can do) in detail, but leaves out the implementation details (how to utilize the capabilities). The idea is to give the designer enough information to evaluate the capabilities, without requiring weeks of study. This paper should create significant enthusiasm in many designers who before did not have the patience or the motivation to study the full-up User Guides.
Like all other Xilinx FPGAs, Virtex-5 FPGAs store their customized configuration in SRAM-type internal latches. The array size is between 8 Mb and 79 Mb (1 to 10 MB), depending on device size but independent of the specific user-design implementation, unless compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROG pin Low. Several methods and data formats for loading configuration are available, determined by the levels on the three Mode pins.
Bit-serial configurations can be either Master Serial where the FPGA generates the configuration clock (CCLK) signal, or Slave Serial where the external configuration data source also clocks the FPGA. For byte- and word-wide configurations, Master SelectMap mode generates the CCLK signal while Slave SelectMap mode receives the CCLK signal for the 8-, 16-, or 32-bit-wide transfer. Alternatively, Serial Peripheral Interface (SPI) and Byte Peripheral Interface (BPI) modes interface with industry-standard flash memories and are clocked by the FPGA's CCLK output. JTAG mode uses Boundary-Scan protocols to load bit-serial configuration data.
The bitstream configuration information is generated by the Xilinx ISE development software using a program called BitGen. The configuration process always executes the following sequence:
- Detects power-up (Power-On Reset) or PROG being Low.
- Clears the whole configuration memory.
- Samples the mode pins to determine the configuration mode. (Master or slave, bit-serial or parallel, etc)
- Loads the configuration data starting with a synchronization word and a check for the proper device code and ending with a cyclic redundancy check (CRC) of the complete bitstream.
- Start-up executes a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the DCMs to lock, activating the output drivers and making DOBE go High.
Dynamic Reconfiguration Port (DRP)
The DRP gives the user easy access to configuration bits and status registers for the following three block types:
- 32 locations for each Clock Tile (both DCM and PLL)
- 128 locations for the System Monitor
- 128 locations for each MGT GTP_DUAL tile
DRP behaves like memory-mapped IO, and can access and modify block-specific configuration bits, as well as status and control registers.
Encryption, Readback, Compression, and Partial Re-configuration
As a special option, the bitstream can be AES-encrypted to prevent unauthorized copying of the design. The Virtex-5 FPGA performs the decryption using the internally stored 256-bit key that can use battery backup to remain non-volatile.
Most configuration data can be read back without affecting the user operation. Configuration data compression takes advantage of repetition in the configuration data structure. In most cases, configuration is an "all-or-nothing" operation, but the Virtex-5 FPGA also supports partial reconfiguration, which in certain designs can greatly improve the versatility of the FPGA, when applicable. It is possible to reconfigure only a portion of the FPGA while the rest of the logic remains active. This operation is called partial reconfiguration.
Subsets of the different logic types such as CLBs, BRAMs, I/Os, etc. can be designated as reconfigurable by using Xilinx PlanAhead and ISE software. A floorplan is created that includes the amount and type of logic required for the hierarchical block of the design that will be partially reconfigured. After the design is implemented, a partial bit file is generated for each component of the design that will be reconfigured.
Downloading the partial bit file is exactly like downloading a full bit file. Simply download the partial bit file to the JTAG, Serial, or SelectMap ports and the FPGA will be partially reconfigured. The Internal Configuration Access Port (ICAP) also supports partial reconfiguration, so that an external interface such as JTAG, Serial, or SelectMap may not be required.
Four-input look-up tables (LUTs) have been the mainstay of the logic fabric in FPGAs for almost 20 years. As advances in technology have made regular structures more space-efficient but interconnects more dominant, LUT capacity has been increased from 16 bits to 64 bits (6 inputs).
The LUTs in Virtex-5 FPGAs can be configured as either 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Four such LUTs and four flip flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a Configurable Logic Block (CLB). Virtex-5 FPGA slices implement multiplexers very efficiently: four 4:1, two 8:1, or one 16:1 multiplexer in any slice. In addition to this, between 25 and 50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools know how to take advantage of these highly efficient features, but expert users can also instantiate them.