With their zero NRE and shorter design cycles, FPGA's are steadily replacing ASIC's in mid-level commercial and even higher-volume consumer applications. But as FPGA usage has steadily grown, so have the problems of designing them into PCB's. The higher pin densities employed in today's larger devices has led to increased routing congestion as more and more signals converge into a smaller and smaller space on the PCB.
In an attempt to alleviate the bottlenecks, design teams struggle with effectively choosing I/O pin assignments that not only work well for the FPGA but which are optimized for the PCB routing. Compounding the problem is the classic EDA tool flow, which requires symbols and schematics to drive the PCB design process. Creating and maintaining this data throughout the FPGA and system-level design cycle can be an exercise in frustration as each change to a signal's location on the periphery of the FPGA can wreak havoc.
Lacking sufficient commercial tools to deal with the issue, many companies attempt to roll their own solutions, assembling combinations of spreadsheets, drawings, text files, and formalized procedures. Constructing and administering these stop-gap measures entails significant effort and actually using them requires an almost myopic attention to detail.
A system-level design process that does not wholly embrace and support the unique ability of an FPGA to individually program its I/O pin characteristics can produce disastrous results. Regrettably, and for numerous reasons, many processes don't. In some, engineers lock the FPGA's pins, thereby forcing PCB designers to fix an un-fixable mess. In others, the pins are never locked and the team struggles to converge on an optimal set of pin assignments.
On the other hand, processes that endorse the dynamic nature of an FPGA's I/O structure can reap substantial benefits. An FPGA can be ideally tuned to the specific board and system it will be used on. Managed well, repositioning signals on the FPGA can be successfully exploited as another weapon in the fight to meet what often appears to be an overwhelming set of conflicting, system-level constraints.
PCB topology effects – physical constraints
Commercial EDA tools that help liberate the full potential of FPGA's – while concurrently bringing order to the I/O planning madness – are sorely needed. Every FPGA design team toils to some degree and in some manner with the burden of creating and managing optimal pin assignments. To illustrate the situation, consider a trivial example: two FPGA's interfacing with four DDR2 memories as illustrated in Fig 1. Given this, what's the best pin assignment for the entire system?
1. One design – three PCB layout options.
(Click this image to view a larger, more detailed version)
The answer is – without at least a crude understanding of the PCB topology – it's impossible to tell! Board-optimal pin assignments cannot be made while simultaneously ignoring the board. But in a misguided, zealous desire to get the job done, many teams regularly allow FPGA designers to do exactly that: pick the pins without completely appreciating the PCB-related ramifications of their decisions. In other words, they discount the physical constraints of the design.
This does one thing: it postpones the inevitable and puts the monkey squarely on the PCB designer's back. The very person that has the least design flexibility is told to "fix it, but don't change anything." The whole process ultimately collapses under its own weight, with predictable and all-too-frequent results: PCB re-spins to correct mistakes found too late, extended design cycles, failure to meet original performance and/or manufacturing goals, and jeopardized market windows.
Another thing to consider is that, for a given design, the right solution may not even be found by focusing simply on better pin assignments, but in modifying the PCB layout to more effectively open up the routing channels. As such, moving the PCB layout process earlier in the design cycle could clearly help improve the overall results.
Many engineers already do this, especially with critical signals. Either by sitting down with the PCB designer and dictating where components need to be placed or by capturing that data in a constraint system, engineers typically do not give PCB designers free reign over the layout. At a minimum, any product or methodology that claims to solve this problem is going to have to take the PCB into account. Beyond that, being able to read and even manipulate the PCB layout early in the cycle, as part of the pin assignment process, would provide significant benefits. In other words, FPGA I/O design needs to be thought of as a system-level problem, not one that can be compartmentalized within a single design discipline.
FPGA usage rules – electrical constraints
A further variable in the pin assignment equation that must be dealt with is the electrical constraints of the FPGA's. While the previous example might look simple, keep in mind that those two FPGA's could easily represent two to three thousand user-configurable pins (imagine tackling a design with four or five – or twenty – FPGA's).
In addition to the constraints that the PCB topology imposes, the sheer number of FPGA pins – each with numerous programmable characteristics – places additional strain on the I/O design process. This is likely a contributing factor in many decisions to disregard the PCB and why it is seldom given its due consideration. Just getting the pins configured correctly so that the FPGA behaves itself electrically can be intimidating. Fortunately, the FPGA vendor's tools can be deployed here, with proven, routine success. Still, those tools operate on a single FPGA at a time and they don't even pretend to acknowledge the existence of a PC board.