With stricter system power limits, specifications and standards that put a cap on the total power consumed, system designers are increasingly challenged. This paper presents the key Dos and Don'ts to help designers manage power budgets with FPGAs.
Do profile your design. How long will the FPGA be running at high speed versus low speed or with stopped clocks?
Can burst mode processing at a higher clock frequency, but with more device "sleep" time, achieve the required system throughput?
Is it better to run the entire design at a lower clock frequency for longer periods of time? Most FPGA suppliers provide power analysis and prediction tools to help in this process; however, some tools can be overly optimisticbe careful.
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