Editor's Note As with similar "lite" user guides published by Programmable Logic DesignLine previously, this guide is intended to bridge the gap between a datasheet and a full, 1,000+ page user guide.
What is the purpose of this paper?
This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Virtex-6 FPGAs. It describes the functionality of these devices in far more detail than in the data sheetbut avoids the minute implementation details covered in the various Virtex-6 FPGA user guides.
In traditional product documentation, a data sheet provides concentrated information about the whole family, without describing the capabilities in great detail. On the other hand, user guides give all the details that the designer needs, but at more than a thousand pages they may require weeks of work to read and understand all the details.
This paper describes the capabilities (what you can do) in detail but leaves out the implementation details (how to utilize the capabilities). The idea is to give the designer enough information to evaluate the capabilities, without requiring weeks of study. This paper should create significant enthusiasm in many designers, who before did not have the patience or the motivation to study entire user guides.
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Virtex-6 FPGAs build on the success of the Virtex-5 family. The more advanced 40 nm process makes it technically and economically possible to more than double the logic capacity of the largest family member (760,000 logic cells, 948,000 flip-flops, and 38 Mb of block RAM, compared to 360,000 logic cells, 207,000 flip-flops, and 18 Mb of block RAM in the largest Virtex-5 FPGA).
Advanced processing, innovative architecture and circuit design, and a lower supply voltage reduce static and dynamic power consumption by over 30%, a surprising feat that is highly appreciated by the user.
Higher performance is also the combined result of better processing, architecture, and tools. Advanced 40 nm processing offers transistors with three different oxide thicknesses and multiple threshold voltages as well as low-K dielectric between interconnect lines.
Architectural improvements center around enhanced LUTs, with more flip-flops and better routing, better clock generation, low-skew clock distribution, faster I/O, and significantly faster 6.5 Gb/s transceivers. Many dedicated system-level blocks offer ASIC-like performance, size, and low power, while they are tightly integrated in a versatile FPGA structure. Finally, improved tools offer much faster synthesis, and place and route of the user's design.