CLBs, Slices, and LUTs
Spartan-6 FPGA Configurable Logic Block User Guide
Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Expert designers can also instantiate them.
One quarter (25%) of Spartan-6 slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a 6 input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register (SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop within the CLB.
For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.
One quarter (25%) of Spartan-6 slices are SLICELs, which contain all the features of the SLICEM except the memory/shift register function.
One half (50%) of Spartan-6 slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the arithmetic carry option and the wide multiplexers.