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Timing Closure on FPGAs

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mohammad.waris
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re: Timing Closure on FPGAs
mohammad.waris   10/30/2010 6:53:03 AM
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@ Dr DSP :) rightly said!!!

DrFPGA
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re: Timing Closure on FPGAs
DrFPGA   8/13/2010 12:15:44 AM
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Another option is to use a synthesis directive. Try "please_don't_mess_up_my_clock_network = 1" After so many person centuries of work why is it synthesis tools don't just override clearly bad design, make a fix, and issue a warning that it has made an improvement. Maybe a PhD thesis for someone out there?

jeffp
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re: Timing Closure on FPGAs
jeffp   6/2/2010 7:00:15 PM
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You can always wrap primitives from multiple venodors in a more generic entity/module. We use generics in VHDL and defines in verilog to specify which technology is chosen when the design is elaborated in synthesis. If no technology is defined it falls through to RTL for simulation

sherry151
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re: Timing Closure on FPGAs
sherry151   5/8/2010 7:42:13 PM
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The vendors will always ask the designers to use primitives which is normally put forward as a good design practice but actually is a marketing strategy, trying to maintain the monopoly as the code can not be used on any other vendor's device, not even on some other device arch of the same vendor. So try to stay away from primitives as much as possible.

IRSSYS
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re: Timing Closure on FPGAs
IRSSYS   4/30/2010 7:39:02 AM
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Could have been a nice article if not the wrong code fragments had been used in several places here...

rysc
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re: Timing Closure on FPGAs
rysc   4/29/2010 5:21:49 PM
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Agreed about the reset. I much prefer an "asynchronous assert/synchronous de-assert" circuit. It's basically two registers chained together. The input to the first register is VCC. The external reset feeds the asynchronous reset of both registers, and the second register fans out to the asynchronous reset port of every register in the same clock domain. You get is an asynchronous assertion of reset, which is critical for many applications that need to be "resettable" in the case of failure, even if the failure is that the clock goes away. (Think of a car accelerating, and if the clock chip breaks, the user needs to be able to reset to a non-accelerating state. Hate to use what's been in the news, but it's a good analogy). The circuit also does a synchronous de-assert, meaning all paths can be timed when coming out of reset, such that all registers start toggling on the same clock edge. As for using primitives, though it may give you what you want, it's at the expense of writing vendor-independent code. The syntheiss tools have become stodgy enough(if that's the right adjective) that these issues hardly ever happen anymore. It's definitely a trade-off, but I find most users find sticking to RTL the better goal in the long-run, then worrying about incorrect/different synthesis.

tato76
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re: Timing Closure on FPGAs
tato76   4/22/2010 10:13:58 AM
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Please be careful when reprinting articless. There is at least one code bit missing and one that hardly readable. One thing about the article itself: I personally don't like the ANDed reset approach. There is a slight chance of metastability because you're AND'ing an asynchronous signal which is the "reset" signal in the example.

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