The Meta system includes comprehensive development tools and a variety of peripheral types.
Like other processor core companies, Metagence combines pre-verified hardware and software IP (intellectual property) elements and development tools, reducing development risk and time to market. Where Meta differs is in the processor structure itself. Similar in concept to the multi-threading proposed by Don Sollars in the now defunct TeraGen product, META supports multiple threads in hardware, with each thread being a virtualized instantiation of the processor, with its own register resources. Using this paradigm enables transparent scaling as hardware capabilities improve with each succeeding semiconductor process generation.
The META Base Architecture Multi-threading allows META to switch contexts in response to real-time events without software
The heart of Meta is the threading mechanism that provides hardware control over the process.
In the event of a condition with the potential to cause a stall cycle, e.g., a cache miss,
META automatically starts executing the next thread. There are times when a specific
thread must run, and to support that, META provides a number of features including cache line
locking and cache pre-fetching to control memory stalls & data address pre-issue to avoid pipeline delays. Metagence calls their threading variant superthreading. All threads operate in a parallel/overlapped manner with no context switching overheads, increasing utilization of shared ALU and cache/memory resources.
Unlike multi-processor systems, where care must be taken early on to partition tasks between
processors, META allows developers to regard the code on each thread as if it is the only code
present, i.e., they can develop real-time applications in isolation, and later run them in parallel on
separate threads, since the details of multi-threading are automatically handled by the META
hardware and software development tools.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.