The building blocks of a digital amplifier are shown in figure A.
Figure A: Digital amplifier
A digital amplifier takes a digital input, which is typically in a linear Pulse Code Modulation (PCM) format, and performs a digital conversion (via a number of steps, described below) to Pulse Width Modulation (PWM). The PWM modulator drives switching FETs to produce a high voltage switched signal, which is then filtered to reproduce the original audio input. The reconstruction of a sine wave from a PWM signal is illustrated in figure B.
Figure B: Recreating a sine wave from PWM
signal amplitude is dependent on the area of the pulses, so for accurate signal reconstruction, both time alignment and rail voltage are critical parameters. Complex audio signals will also cause intermodulation via the power supplies unless a very low impedance supply is used.
The PWM signal is generated digitally and therefore the pulse widths are quantized. Practical considerations in the power output stage limit the maximum switching frequency (fsw), although higher frequencies allow easier filtering of switching noise in the reconstruction filter. The resolution in the PWM waveform is dependent on the ratio of the Master Clock (MCK) frequency to the switching frequency, which is usually a power of 2.
The digital PCM input is also quantized: a resolution of 32 bits gives a theoretical 194dB dynamic range, if limited solely by quantization noise. More practically, 24 bits (the best resolution of today's audio ADCs) has a theoretical 144 dB dynamic range.
The PWM resolution is typically much more coarse, in order to keep switching frequency above maximum audio sample rates of 192 kHz, whilst limiting MCK frequency. Typical ratios are between 32 (5 bits) and 256 (8 bits), giving a best dynamic range of 50 dB. Clearly, this means that other techniques are required to provide sufficient dynamic range, and the answer is oversampling with noise shaping. This technique essentially allows a time averaging of the PWM pulse widths to be applied, to deliver fractional resolution in the amplitude of the output signal.
The MCK of a digital amplifier, which needs a low jitter specification for good amplifier performance, will either need to be a fixed multiple of the incoming sample rate or else can be a fixed crystal generated frequency. The first case requires a phase locked loop, which is often a source of jitter. In the second case, a sample rate converter is required to re-align the incoming oversampled data with the MCK period.
Both oversampling and sample rate conversion use interpolation and averaging filters, requiring a large number of multiply accumulates, and hence MCK cycles, which add up to a signal group delay that is significant at audio frequencies. The delay is fixed and so affects the phase of all input signal frequencies linearly, which is benign in audio terms, but must be borne in mind for any feedback system comparing output with input.
So, key system considerations for a digital amplifier are:
Power supply purity and impedance
PWM switching speed and resolution
Master clock frequency and jitter
Group delay of the processed signal
About the author:
David E.L.Jones, Audio Systems Engineer at Zetex Semiconductors for 3 years, has been involved in audio and signal processing since 1983 when he worked on the first professional CD players, building on his power electronics experience and lifelong passion to design superior audio amplifiers. He holds a BSc in Mathematics and is a member of the AES.