# Using Op Amps with Data Converters - Part 2

*[Part 1 offers an introduction to selecting op amps for use with data converters.]*

**ADC and DAC Static Transfer Functions and DC Errors**

The most important thing to remember about both DACs and ADCs is that either the input or output is digital, and therefore the signal is *quantized*. That is, an N-bit word represents one of 2^{N} possible states, and therefore an N-bit DAC (with a fixed reference) can have only 2^{N} possible analog outputs, and an N-bit ADC can have only 2^{N} possible digital outputs. The analog signals will generally be voltages or currents.

The resolution of data converters may be expressed in several different ways: the weight of the Least Significant Bit (LSB), parts per million of full scale (ppm FS), millivolts (mV), and so forth. It is common that different devices (even from the same manufacturer) will be specified differently, so converter users must learn to translate between the different types of specifications if they are to successfully compare devices. The size of the least significant bit for various resolutions is shown in Figure 3-5.

As noted above (and obvious from this table), the LSB scaling for a given converter resolution can be expressed in various ways. While it is convenient to relate this to a full scale of 10 V, as in Figure 3-5, other full scale levels can be easily extrapolated.

Before we can consider op amp applications with data converters, it is necessary to consider the performance to be expected, and the specifications that are important when operating with data converters. The following sections will consider the definition of errors and specifications used for data converters.

The first applications of data converters were in measurement and control, where the exact timing of the conversion was usually unimportant, and the data rate was slow. In such applications, the dc specifications of converters are important, but timing and ac specifications are not. Today many, if not most, converters are used in *sampling* and *reconstruction* systems where ac specifications are critical (and dc ones may not be).

Figure 3-6 shows the transfer characteristics for a 3-bit unipolar ideal and nonideal DAC. In a DAC, both the input and output are quantized, and the graph consists of eight points—while it is reasonable to discuss a line through these points, it is critical to remember that the actual transfer characteristic is *not* a line, but a series of discrete points.

Similarly, Figure 3-7 shows the transfer characteristics for a 3-bit unipolar ideal and nonideal ADC. Note that the input to an ADC is analog and is therefore *not* quantized, but its output *is* quantized.

The ADC transfer characteristic therefore consists of eight horizontal steps (when considering the offset, gain and linearity of an ADC we consider the line joining the midpoints of these steps).

The (ideal) ADC transitions take place at ½ LSB above zero, and thereafter every LSB, until 1½ LSB below analog full scale. Since the analog input to an ADC can take any value, but the digital output is quantized, there may be a difference of up to ½ LSB between the actual analog input and the exact value of the digital output. This is known as the quantization error or quantization uncertainty as shown in Figure 3-7. In ac (sampling) applications this quantization error gives rise to quantization noise which will be discussed shortly.

The *integral linearity* error of a converter is analogous to the linearity error of an amplifier, and is defined as the maximum deviation of the actual transfer characteristic of the converter from a straight line. It is generally expressed as a percentage of full scale (but may be given in LSBs). There are two common ways of choosing the straight line: *end point* and *best straight line*.

In the end point system, the deviation is measured from the straight line through the origin and the full scale point (after gain adjustment). This is the most useful integral linearity measurement for measurement and control applications of data converters (since error budgets depend on deviation from the ideal transfer characteristic, not from some arbitrary "best fit"), and is the one normally adopted by Analog Devices, Inc.

The best straight line, however, does give a better prediction of distortion in ac applications, and also gives a lower value of "linearity error" on a data sheet. The best fit straight line is drawn through the transfer characteristic of the device using standard curve fitting techniques, and the maximum deviation is measured from this line. In general, the integral linearity error measured in this way is only 50% of the value measured by end point methods. This makes the method good for producing impressive datasheets, but it is less useful for error budget analysis. For ac applications, it is even better to specify distortion than dc linearity, so it is rarely necessary to use the best straight line method to define converter linearity.

The other type of converter nonlinearity is *differential nonlinearity* (DNL). This relates to the linearity of the code transitions of the converter. In the ideal case, a change of 1 LSB in digital code corresponds to a change of exactly 1 LSB of analog signal. In a DAC, a change of 1 LSB in digital code produces exactly 1 LSB change of analog output, while in an ADC there should be exactly 1 LSB change of analog input to move from one digital transition to the next.

Where the change in analog signal corresponding to 1 LSB digital change is more or less than 1 LSB, there is said to be a DNL error. The DNL error of a converter is normally defined as the maximum value of DNL to be found at any transition.

If the DNL of a DAC is less than "1 LSB at any transition (Figure 3-6), the DAC is *nonmonotonic*; i.e., its transfer characteristic contains one or more localized maxima or minima. A DNL greater than +1 LSB does not cause nonmonotonicity, but is still undesirable. In many DAC applications (especially closed-loop systems where nonmonotonicity can change negative feedback to positive feedback), it is critically important that DACs are monotonic. DAC monotonicity is often explicitly specified on datasheets, but if the DNL is guaranteed to be less than 1 LSB (i.e., |DNL| = 1LSB) then the device must be monotonic, even without an explicit guarantee.

ADCs can be nonmonotonic, but a more common result of excess DNL in ADCs is *missing codes* (Figure 3-7). Missing codes (or nonmonotonicity) in an ADC are as objectionable as nonmonotonicity in a DAC. Again, they result from DNL > 1 LSB.