[Part 1 offers an overview and introduction to the sources of distortion in audio power amplifiers. Part 2 focuses on distortion in the audio amplifier input stage. Part 3 examines distortion mechanisms in the voltage amplifier stage (VAS). Part 4 focuses on distortion in the audio power amplifier output stage. Part 5 continues the discussion of distortion in the power amplifier output stages. Part 6 looks at some of the remaining distortion mechanisms in audio power amplifiers.]
The distortion performance of an amplifier is determined not only by open loop linearity, but also the negative feedback factor applied when the loop is closed. In most practical circumstances doubling the NFB factor halves the distortion.
To date, this series has focused on basic circuit linearity. I have assumed that open loop gain falls at 6 dB/octave due to a single dominant pole, with the amount of NFB permissible at HF being set by the demands of HF stability. Because of this, the distortion residuals from a 'blameless' amplifier are comprised almost entirely of crossover artifacts due to their high frequency content. Audio amplifiers using more advanced compensation are rather rare. However, certain techniques do exist ...
This series has stuck close to conventional topologies, because even commonplace circuitry has been shown to have little known aspects and interesting possibilities. This implies a two-gain-stage circuit (unity gain output stages not being counted) with most of the feedback applied globally, but smoothly transferred to the voltage amplifier stage alone as frequency increases.
Other configurations are possible; a one stage amplifier is an intriguing possibility " they are common in cmos op-amps " but is probably ill-suited to power amp impedances. See Ref. 1 for an eccentric three-stage amplifier with an open loop gain of just 52 dB (due to the dogged use of local feedback) and only 20 dB of global feedback. Most of the section below refers only to the conventional two-stage structure.
Making a pole dominant
Dominant pole compensation is the simplest kind, though its implementation involves subtlety. Simply take the lowest pole to hand (PI), and make it dominant, i.e. so much lower in frequency than the next pole P2 that the total loop gain (the open loop gain as reduced by the attenuation in the feedback network) falls below unity before enough phase shift accumulates to cause HF oscillation. With a single pole, the gain must fall at 6 dB/octave, corresponding to a constant 90° phase shift. Thus the phase margin will be 90° giving good stability. Figure 1(a) shows the traditional Miller method of making a dominant pole.
Figure 1: Implementing dominant-pole compensation. (a) Miller capacitor, (b) Shunt-lag circuit (c) Output-stage Inclusive Miller compensation. (d) How to implement 2-pole compensation.
The collector pole of Tr4 is lowered by adding the Miller capacitance Cdom to that which unavoidably exists as the Cbc of the VAS transistor. However there are other beneficial effects; Cdom causes 'pole splitting', in which the pole at Tr2 collector is pushed up in frequency as P1 moves down " most desirable for stability. Simultaneously the local NFB through Cdom linearises the VAS.
Assuming that input stage transconductance is set to a plausible 5 mA/V, and stability considerations set the maximal 20 kHz open loop gain to 50 dB, then from the equations in Part 1, Cdom must be 125 pF. This is more than enough to swamp the internal capacitances of the VAS transistor, and is a realistic value.
The peak current that flows in and out of this capacitor for an output of 20 V r.m.s., 20 kHz, is 447 µA. Recalling that the input stage must sink Cdom current while the VAS collector load sources it, and likewise the input stage must source it while the VAS sinks it, there are four possible places in which slew rate might be limited by inadequate current capacity. If the input stage is properly designed then the usual limiting factor is VAS current sourcing. In this example a peak current of less than 0.5 mA should be easy to deal with, and the maximum frequency for unslewed output will be comfortably above 20 kHz.
Figure 1(b) shows a much less satisfactory method " the addition of capacitance to ground from the VAS collector. This is usually called shunt lag compensation, and as Peter Baxandall aptly put it, 'The technique is in all respects sub-optimal'.2
We have already seen in Part 3 that loading the VAS collector resistively to ground is a very poor option for reducing LF open loop gain, and a similar argument shows that capacitive loading to ground for compensation purposes is an even worse idea. To reduce open loop gain at 20 kHz to 50 dB as before, the shunt capacitor Clag must be 43.6 nF, which is a whole different order of things from 125 pF. The current flowing in Clag at 20 V r.m.s., 20 kHz, is 155 mA peak, which is going to require some serious electronics to provide it. This important result can be derived by simple calculation, and I have confirmed it with Spice simulation. The input stage no longer constrains the slew rate limits, which now depend entirely on the VAS.
A VAS working under these conditions is almost certain to have poor linearity. The current variations in the stage, caused by the extra loading, produces more distortion and there is now no local NFB through a Miller capacitor to correct it. To make matters worse, the dominant pole P1 will probably need to be set to a lower frequency than for the Miller case, to maintain the same stability margins, as there is now no pole splitting to raise the pole at the input stage collector. Hence Clag may have to be even larger, and require even higher peak currents. Takahashi has produced a fascinating paper on this approach,3 showing one way of heaving about the enormous compensation currents required for good slew rates. The only thing missing is an explanation of why shunt compensation was chosen in the first place.