[Part 1 looks at the overall supply impedance seen by a component when the decoupling caps, the voltage regulator and the board traces are taken into account.]
Previously on "Yet more..." we built up a pair of regulators with output capacitors, and connected them to some decoupling caps with a short length of copper trace. We looked at the impedance at these decoupling caps, and saw some peaks. What happens when we start taking some current from these imperfect supplies?
Figures 2.1 and 2.2 show what happens in the time domain when we take a square wave current switching between 0 and +10mA at 100kHz from the positive regulator, and one switching between -10mA and 0 on the negative regulator. The rationale is that later on, we'll either be taking current from the +ve rail, or dumping it into the -ve rail. Remember that the regulators have a static load of 20mA as well, so we are not taking regulator current down to zero. The swept parameter is once again the value of the local decoupling capacitor, 22nF (top trace, blue) to 470nF (bottom trace, pink), and the traces are offset from the top down by 10mV each time.
Figure 2.1: pinging the positive rail with 100kHz 0 to +10mA square wave, 5mV/div, traces spread by 10mV.
Figure 2.2: pinging the negative rail with 100kHz 0-10mA square wave, 5mV/div, traces spread by 10mV.
As expected, the smallest capacitor shows the highest amplitude of additional ringing, occurring at the highest frequency. As the capacitor value goes up, the magnitude of the ringing falls. Constant in all this is the effective impedance at the 100kHz fundamental, which seems to be about 0.7Ω for either supply. Note that these voltages are in phase. The frequent assumption about the supply variations being symmetrical around ground is not true in this case; indeed, hardly ever true.
The high-frequency ringing looks unsightly and may well impact our circuits - what could we do about that? We need some damping somewhere, perhaps by adding some series resistance to one of the capacitors. This will help to dissipate stored energy in the resonant circuits more rapidly, reducing the 'Q'. Now, with other regulator designs we might have been forced to have this extra series resistance, because some LDO designs are not stable when the main output capacitor has too low an ESR. Often in those designs a tantalum capacitor is used, so let's pick one.
AVX have another useful utility on their download page, SpiTanII, which assists with the selection of tantalum capacitors, and the associated SPICE library contains models which accurately portray the frequency-dependent loss of that type of cap. This should lead to much more accurate simulation than just guessing a resistive ESR value. A 2.2µF 1206-sized part (TPSA225K016R1800 (see data sheet), same footprint as the ceramic previously deployed, and with 16V working voltage) was chosen; it has a rated maximum ESR of 1.8Ω at 100kHz, which is about as good as it gets for a small tantalum. Important tip: fit this capacitor the right way round in your simulations. In the simulation world as well as in the real world, the tantalum capacitor doesn't work properly under reverse polarity!
Figure 2.3: same as fig 2.1 but using a 2.2µF tantalum output cap on the +ve regulator.
Figure 2.4: impedance plots of the supply rails with tantalum capacitors. Contrast with figure 1.2 in Part 1.
What a difference; a lot less high-frequency rubbish (especially on the -ve rail which is not shown). The impedance curves show why; with the tantalum capacitor, the +ve regulator particularly is still showing some peaking just below 1MHz. Still, looks like an improvement, but we will keep testing this choice in the work to come, to see what consequences the ringing has.