# Jitter, Noise, and Signal Integrity at High-Speed: A Tutorial--Part II

**Nonintrinsic Noise and Jitter**

Nonintrinsic jitter and noise are design-related deviations. In other words, those types of jitter and noise can be controlled or fixed with appropriate design improvements. Commonly encountered nonideal design-related noise and jitter include periodic modulation (phase, amplitude, and frequency), duty cycle distortion (DCD), intersymbol interference (ISI), crosstalk, undesired interference such as electromagnetic interference (EMI) due to radiation, and reflection caused by unmatched media. The following sections discuss these noise sources and their root causes.

*Periodic Noise and Jitter*

Periodic noise or jitter is a type of signal that repeats every time period. It can be described mathematically by the following general equation:

where T_{0} is the period, t is the time, and Φ_{0} is the phase of the periodic signal. The period T_{0} and frequency f_{0} satisfy the reciprocal relationship of T_{0} = 1/f_{0}. Although the notation and discussion are based on timing jitter, the same type of discussion can be applied to amplitude noise. The frequency-domain periodic function can be obtained through Fourier Transformation (FT), a subject that is discussed in Chapter 2, "Statistical Signal and Linear Theory for Jitter, Noise, and Signal Integrity."

Periodic jitter can be caused by various modulation mechanisms, such as amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM). Moreover, the modulation function can have various shapes. Typical modulation shapes include sinusoidal, triangular, and sawtooth. It is apparent that a periodic amplitude noise causes period timing jitter, with the amplitude proportional inversely to the slope or slew rate of the edge transition. In the computer environment, period noise/jitter can be caused by switching power supply, spread-spectrum clock (SSC), and period EMI sources.

*Duty Cycle Distortion (DCD)*

DCD is defined as the deviation in duty cycle from its normal value. Mathematically, a duty cycle is the ratio of pulse width to its period for a clock signal, as shown in Figure 6.

_{0}), pulse width PW

_{+}/PW

_{"}(either positive or negative), and reference level for a periodic signal.

Duty cycle is defined as follows:

Most clocks have a nominal duty cycle of 50%. So either shorter pulse width or longer pulse width causes DCD. DCD can be caused by pulse width deviation, period deviation, or both. Furthermore, pulse width deviation can be caused by the deviation of reference signal level. Another DCD-causing mechanism is propagation delay if the clock is formed from rising and falling edges of two half-rate clocks and those two half-rate clocks undergo different propagation delays. Because a clock can have many periods, DCD must be looked at from the distribution point of view with many samples considered, and the average period should be used for the overall DCD estimation.

*Intersymbol Interference (ISI)*

ISI is related to data signal, but a clock signal does not have ISI by definition. A data signal is a generic digital signal form that does not have to have an edge transition in every UI or bit period, like the clock signal. The data signal can be kept at the same amplitude level for many UIs without an edge transition, whereas a clock signal cannot be. The type of data pattern used in digital communication critically depends on the coding scheme of the communication architecture.^{9} An important parameter for digital pattern is the run length, which is defined as the maximum length of consecutive 1s or 0s within a pattern. The run length determines the lowest frequency of the data pattern spectrum and therefore governs the frequency range for the test coverage. The long-haul fiber-optic communication standard SONET uses a scramble code scheme and can have a much longer run length (such as a run length of 23, 31) and therefore relatively low-frequency spectral content. A short-haul data communication standard such as Fibre Channel or Gigabit Ethernet uses block code (e.g, 8B10B coding) that has a shorter run length (e.g., a run length of 5) and relatively high-frequency spectral content.

In a lossy medium, the previous bits can cause both transition timing and amplitude level off the ideal values. In copper-based communication systems, this is due to the "memory" characteristics of the electronic devices used to switch bits between 1s and 0s. One example of this "memory" nature is the capacitive effect. Due to capacitive effect, each transition has a finite charge or discharge time. If the transition happens such that the next transition occurs before the previous transition reaches the designated level, deviation of both time and level occurs for the current bit. Such an effect can be cascaded. The ISI effect is shown in Figure 7.