Order this book today and receive an additional 20% discount. Click here: Elsevier Direct and make sure to type in 92351 when ordering this book. Or call 1-800-545-2522 and be sure to mention 92351 when ordering. Offer expires 06/01/08 and the offer is valid only in North America.
Review: Part I and Part II
Hierarchy of Energy Conservation Techniques
The approach to Energy conservation is a holistic approach which includes process technology, packaging, circuit and module design, System-on-a-Chip (SoC) design, tools, and system and application software to efficiently utilize the energy available to the system.
The last quarter century has seen enormous progress in the performance and capabilities of servers, desktop computers, laptops, and handheld devices. These gains have only increased the hunger for faster operation, greater functionality, lower prices, and smaller, more portable form factors.
Designing for energy-efficient performance is a paramount to ensure that new systems can support high-end applications without dramatically increasing energy consumption. This requires a fundamental rethinking on how to deliver new levels of performance within a given power envelope.
In order to deliver such energy-efficient platforms, a holistic effort is required across all common platform components including software, processors, hard drives, power supplies, radios, displays, and more. A holistic approach must include advanced power efficient micro architectures, industry-leading silicon technologies, and manufacturing expertise, world-class research, power-aware technologies, and unmatched ecosystem-building capabilities (packaging, software, tools, etc.). Table 1 indicates some the specific techniques applied at the various levels of design.
A common approach to solve the complex power management problems that involve massive amounts of data is to break down the problem into manageable pieces and solve one piece at a time. If the pieces are small enough, the overall problem can be manageable. Of course, the trick is to bring all of the pieces together again and provide the answer to the original problem. This final integration stage is often overlooked and great implemented technology fails to deliver its promise due to an organizational oversight.
This approach has long been applied to complex engineering projects and is now finding its way into low power design. Hierarchical design can be roughly separated into three broad categories: planning, implementation, and assembly. Planning, often called "top-down" design, is the process of breaking the overall design into blocks that will be implemented individually. Planning is critical, because it sets the baseline for the entire project and must yield a final design that meets the project goals for timing, size, power, and other requirements (Figure 5).
Figure 5. Hierarchical Design
Implementation and assembly, sometimes referred to as "bottom-up" design, is the process of implementing the detailed design of the individual blocks. Assembly is the process of connecting all of the blocks in the design to result in the final product. In this process, there are often preexisting IP blocks (such as memories, cores, etc.) that need to be considered during the planning process and added to the design during the assembly process. Also, it is more efficient to add "glue logic" during the assembly of the final chip, rather than structure it has a separate block that needs to be implemented during the bottom-up process.
Design teams develop and adopt hierarchical flows for many reasons. Complexity management and the need to shorten the turnaround time on large designs are usually at the top of the list. Using a hierarchical flow, the design can be attacked by different teams in different locations, resulting in concurrent engineering of the overall product.
In addition, SoC design and intellectual property (IP) reuse methodologies also demand a hierarchical approach to chip design, because they involve bringing preexisting blocks into the design process. Figure 6 illustrates an example of an SoC block diagram and the various modules that comprise the SoC.
Figure 6. A Typical SoC Block Diagram (Source: i.MX Integrated Portable System Processor, www.freescale.com)