[Editor's note: The Ambric architecture is similar to the architecture of the Intellasys
SEAforth processor. For a detailed article explaining the advantages of these architectures, see 21st century multiprocessor design.]
On August 21st fabless semiconductor startup Ambric unveiled its massively parallel processor architecture. Ambric joins a host of start-ups pursuing a similar idea: chaining together a large number of simple RISC-like processor cores in ways intended to avoid inter-processor communication bottlenecks and programming problems found in traditional multiprocessor systems. In the Ambric architecture, individual processors can run at different clock speeds, and processors operate asynchronously relative to each other. Asynchronous hardware channels coordinate communication between processors at run-time, avoiding the need for a global synchronization scheme.
"At Ambric, we believed the key to a practical solution for massively parallel embedded computing was the unrelenting focus on first developing the right programming model. After developing that model, we then invented new hardware architectures and circuit designs to enable it," explains Mike Butts, senior IC architect at Ambric. As illustrated in Figure 1, to implement an application, the developer decomposes his application into a hierarchical structure of basic tasks, or "objects" in Ambric's nomenclature, specifying the data and control messages each object sends and receives. Objects are then implemented using a conventional compiler and debugged using a functional simulator. When the objects have been implemented and verified, a realization tool chain is run which maps the objects onto processors and memories, routes the interprocessor communications, and creates a configuration file for the chip. The chip is configured upon start-up much like an FPGA, with the configuration file being read from flash or supplied by an external host. Once the chip is configured, real-time debugging is enabled by employing unused processors and memories to monitor channel traffic.
1. Example hierarchical grouping of Ambric "objects"
For BDTI's analysis of the Ambric architecture, see Inside DSP.