It should not come as news or a surprise to engineers that design cycles are short, product cost is an issue, and getting it right the first time is still the goal. It is also well-known that the ever changing standards, increased design complexities, high NRE and design re-spin charges, and lack of seamless tool flows are making it that much harder to meet the time-to-market and cost objectives.
In particular, for implementation of signal processing systems on FPGAs and ASICs, engineers are well aware that there is significant overlap between system design, HDL design, and verification tasks. Yet, tools to seamlessly integrate these tasks are lacking. For example, system engineers and HDL engineers are still engaged in a manual 'bit-true' verification methodology. This is often a laborious, time consuming, and error-prone activity involving file exchanges between the system designer and the HDL designer. Geographically diverse teams face even bigger challenges in this regard since the system designer and the HDL designers are not sitting in the same location.
What is needed, then, is a design methodology that bridges the world of system designers, the HDL designers, and verification engineers to increase productivity and produce 'correct-by-construction' designs that match the system specification.
This paper will illustrate how the process of Model-Based Design provides the benefits of top-down and bottom-up design methodologies to help quickly achieve the design objectives. Using the concept of 'golden design specification,' the paper will discuss how Model-Based Design streamlines both design and verification of HDL implementations.
As the complexity of designs has increased, the system designers have moved testability to the forefront of the design cycle. Today, most design specifications require verification and test methodology to be included as part of the original design document. This is a good trend.
As Figure 1 shows many of the flaws that are introduced in the design specification are captured at a much later stage in the design cycle. 
Finding and fixing design flaws early in the design cycle would clearly lead to much improved designs and the likelihood of designs that reach their target market on time.
Figure 1. Errors are introduced early in the design process but caught much later. 
In a recent EE Times survey, it was noted that system design consumes 18% of the design schedule, followed by 20% time spent in HDL design, and 28% time spent in functional verification.  That represents nearly 2/3 of the design schedule. It would seem natural, then, to look for productivity gains early in the design process.
About Design Methodologies
Real productivity gains can be realized by choosing the right design methodology. Software designers quite often use top-down design methodology to quickly create a working model of their design. In the early days of IC design, hardware engineers also used top-down design methodology.
In top-down design methodology, individual blocks are designed and verified within the context of the top-level. This is beneficial because the block level interfaces and functionality are both verified at the top-level. In this design flow, there is only one test bench and the number of synthesis and simulation scripts is minimized. Moreover, there is the added benefit of script portability across projects.
However, the nature of top-down design is such that the entire design can only be simulated at the top level and block-level verification done at the top-level is an inefficient way to use verification time. In addition, the HDL simulation speed is very slow and powerful machines are required to achieve decent simulation time.
Driven in part by the desire to speed-up simulation time and part by the desire to verify blocks before they are used, engineers adopted bottom-up design methodology. In bottom-up design methodology, the blocks are designed and verified individually before they are integrated together to create the top level system.
Experienced engineers will recognize that bottom-up design introduces a lot of rework into the design process and, in most cases, the test structures that are built to verify individual blocks are not reusable for top level verification. Moreover, the rework shows up at the most inopportune time. That is, it often becomes necessary to redesign blocks when the top level system is put together and engineers realize that the blocks don't integrate as specified in the original specification.
Two engineers reading the same specification may have different interpretation or the specification may have been incorrect to begin with. Whatever the cause, by the time top level integration takes place, schedule deadlines become increasingly critical. At this point either the offending blocks, which have been painstakingly verified at the block level by the designer, must be redesigned or a 'patch' is put in place. Neither is an optimal solution.
Clearly, to counter this increased system complexity and compressed design cycles, a new methodology is needed that captures the benefits of top-down and bottom-up design methodologies. Recent advances in co-simulation technologies have enabled fast simulation time and verification of individual blocks in a system environment. The rest of this paper discusses how engineers can implement a practical and scalable design environment that offers the combined benefits of top-down and bottom-up design flows using MATLAB, Simulink, and Link for ModelSim.