[Part 4 explains how flash converter and subranging (i.e., pipelined) ADCs work.]
Bit-Per-Stage (Serial or Ripple) ADCs
Various architectures exist for performing A/D conversion using one stage per bit. In fact, a multistage subranging ADC with one bit per stage and no error correction is one form. Figure 3-28 shows the overall concept. The SHA holds the input signal constant during the conversion cycle. There are N stages, each of which have a bit output and a residue output. The residue output of one stage is the input to the next. The last bit is detected with a single comparator as shown.
Figure 3-28: Bit-Per-Stage, Serial, or Ripple ADC.
The basic stage for performing a single binary bit conversion is shown in Figure 3-29. It consists of a gain-of-two amplifier, a comparator, and a 1-bit DAC. Assume that this is the first stage of the ADC. The MSB is simply the polarity of the input, and that is detected with the comparator, which also controls the 1-bit DAC. The 1-bit DAC output is summed with the output of the gain-of-two amplifier. The resulting residue output is then applied to the next stage. In order to better understand how the circuit works, the diagram shows the residue output for the case of a linear ramp input voltage that traverses the entire ADC range, –VR to +VR. Notice that the polarity of the residue output determines the binary bit output of the next stage.
Figure 3-29: Single Stage of Binary ADC.
A simplified 3-bit serial-binary ADC is shown in Figure 3-30, and the residue outputs are shown in Figure 3-31. Again, the case is shown for a linear ramp input voltage whose range is between –VR and +VR. Each residue output signal has discontinuities that correspond to the point where the comparator changes state and causes the DAC to switch. The fundamental problem with this architecture is the discontinuity in the residue output waveforms. Adequate settling time must be allowed for these transients to propagate through all the stages and settle at the final comparator input. The prospects of making this architecture operate at high speed are therefore dismal.
Figure 3-30: 3-Bit Serial ADC with Binary Output.
Figure 3-31: Input and Residue Waveforms of 3-Bit Binary Ripple ADC.