For more on Serial RapidIO, see The RapidIO High-Speed Interconnect: A Technical Overview, Easy multiprocessor design with sRIO and MSGQ, and Partitioning video across multiple DSPs and FPGAs.
Today's ever increasing demand for high-speed communication and super-fast computing in support of "triple-play" applications is creating new challenges for system developers, algorithm developers and hardware engineers alike who need to draw together a multitude of standards, components and networking equipment. At the same time, developers need to keep pace with increasing demands for performance while keeping costs low. These feats can be accomplished by leveraging Serial RapidIO-enabled FPGAs as DSP co-processors.
Because triple-play applications unite voice, video and data, development and system optimization strategies must be parameterized using newer algorithms. Specific challenges that developers need to address include building scalable and extensible architectures, supporting distributed processing, using standards-based design, and optimizing for performance and cost.
A closer look at these challenges reveals two themes: Connectivity—which is essentially "fast" data movement across devices, boards and systems—and Computing power—i.e., the individual processing resources that are available in the devices, boards and systems—address the needs of the application.
Connectivity across compute platforms
Standards-based designs are usually much easier than "roll your own" designs, and are the norm of the day. Parallel connectivity standards (PCI, PCI-X, EMIF, etc) can meet today's demands, but fall short when scalability and extensibility are taken into consideration. With the advent of packet-based processing, the trend is clearly towards high-speed serial connectivity. Figure 1 illustrates this trend.
(Click to enlarge)
Figure 1. Trend towards serial connectivity
High speed serial standards like PCIe and GbE/XAUI have been adopted in the desktop and networking industry. Meanwhile, data processing systems in wireless infrastructure have slightly different interconnect requirements:
- Low pin count
- Backplane and chip-to-chip connectivity
- Bandwidth and speed scalability
- DMA and message passing
- Support for complex scalable topologies
- High reliability
- Time of day synchronization
- Quality of Service (QoS)
The Serial RapidIO (SRIO) protocol standard can easily meet and exceed most of these requirements and has become the dominant interconnect for data-plane connectivity in wireless infrastructure equipment. SRIO networks are built around two "Basic Blocks" – Endpoints and Switches. Endpoints source and sink packets, while Switches pass packets between ports without interpreting them. Figure 2 shows SRIO network building blocks.
Figure 2. SRIO network building blocks
Serial RapidIO is specified as a 3-layer architectural hierarchy, illustrated in Figure 3. It has the following elements
Physical Layer—describes the device-level interface specifics such as packet transport mechanisms, flow control, electrical characteristics, and low-level error management.
Transport Layer—provides routing information for moving packets between endpoints. Switches operate at the transport layer by using device-based routing.
Logical Layer—defines the overall protocol and packet formats. All packets contain 256 payload bytes or less. The transactions use Load, Store, or DMA operations targeting a 34 / 50 / 66-bit address space.
For detailed information on the RapidIO specifications, please refer to: http://www.rapidio.org/specs/
(Click to enlarge)
Figure 3. SRIO architecture