# DACs for DSP, part 3: Direct digital synthesis (DDS)

*Part 1 describes the basic structures of digital-to-analog convertors. Part 2 looks at interpolating DACs and sigma-delta DACs.*

**Direct Digital Synthesis (DDS)**

A frequency synthesizer generates multiple frequencies from one or more frequency references. These devices have been used for decades, especially in communications systems. Many are based upon switching and mixing frequency outputs from a bank of crystal oscillators. Others have been based upon well-understood techniques utilizing phase-locked loops (PLLs). This mature technology is illustrated in Figure 13. A fixed-frequency reference drives one input of the phase comparator. The other phase comparator input is driven from a divide-by-N counter which, in turn, is driven by a voltage-controlled oscillator (VCO). Negative feedback forces the output of the internal loop filter to a value that makes the VCO output frequency N-times the reference frequency. The time constant of the loop is controlled by the loop filter. There are many trade-offs in designing a PLL, such as phase noise, tuning speed, and frequency resolution; and there are many good references on the subject (see References 1, 2, and 3).

*Figure 13. Frequency Synthesis Using Oscillators and Phase-Locked Loops*

With the widespread use of digital techniques in instrumentation and communications systems, a digitally controlled method of generating multiple frequencies from a reference frequency source has evolved, called direct digital synthesis (DDS). The basic architecture is shown in Figure 14. In this simplified model, a stable clock drives a programmable read-only memory (PROM) that stores one or more integral number of cycles of a sine wave (or other arbitrary waveform, for that matter). As the address counter steps through each memory location, the corresponding digital amplitude of the signal at each location drives a DAC, which in turn generates the analog output signal. The spectral purity of the final analog output signal is determined primarily by the DAC. The phase noise is basically that of the reference clock.

*Figure 14. Fundamental Direct Digital Synthesis System*

The DDS system differs from the PLL in several ways. Because a DDS system is a sampled data system, all the issues involved in sampling must be considered, including quantization noise, aliasing, and filtering. For instance, the higher order harmonics of the DAC output frequencies fold back into the Nyquist bandwidth, making them unfilterable, whereas the higher order harmonics of the output of PLL-based synthesizers can be filtered. Other considerations will be discussed shortly.

A fundamental problem with this simple DDS system is that the final output frequency can be changed only by changing the reference clock frequency or by reprogramming the PROM, making it rather inflexible. A practical DDS system implements this basic function in a much more flexible and efficient manner using digital hardware called a numerically controlled oscillator (NCO). A block diagram of such a system is shown in Figure 15.

*Figure 15. A Flexible DDS System*

The heart of the system is the *phase accumulator* whose contents are updated once each clock cycle. Each time the phase accumulator is updated, the digital number, M, stored in the *delta phase register* is added to the number in the phase accumulator register. Assume that the number in the delta phase register is 00…01 and that the initial contents of the phase accumulator are 00…00. The phase accumulator is updated by 00…01 on each clock cycle. If the accumulator is 32 bits wide, 2^{32} clock cycles (over 4 billion) are required before the phase accumulator returns to 00…00, and the cycle repeats.