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Asynchronous DSPs: Low power, high performance

5/1/2008 07:00 AM EDT
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scottj
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re: Asynchronous DSPs: Low power, high performance
scottj   5/14/2008 2:58:53 PM
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Ah, but now I see your concerns are those of power consumption, not glitches due to noise. I can't comment on that. Scott

scottj
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re: Asynchronous DSPs: Low power, high performance
scottj   5/14/2008 2:12:55 PM
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Leakage does not impact the logical performance of NCL circuits. The 4-phase handshake protocol and the hysteresis of the m-of-n threshold gate on which NCL is based guarantee this. Not even an EMP blast could alter the logical behavior of the circuit. It would simply wait until the noise dissipates enough to continue. Scott

AlanLevi
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re: Asynchronous DSPs: Low power, high performance
AlanLevi   5/7/2008 5:50:08 PM
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Kenton and James, Thank you for your responses. These confirm what I have suspected for some time now: 1. Clockless logic is still useful at increasingly small geometries. 2. The degree to which clockless logic is useful for reducing power consumption becomes a smaller factor at increasingly small geometries. This is because leakage current becomes such a big factor and therefore is likely to drive design decisions. The remark about clockless circuits being larger as a cause of increases in leakage current is certainly a cause of concern (e.g. for NCL logic). And I understand the rebuttal to this as a valid one: that some flavors of clockless logic do not require additional chip real estate. It seems to me that the leakage issue for smaller geometries is a factor that will greatly hinder widespread adoption of clockless logic in any flavor. This is a direct cause and effect only for some flavors of clockless logic. For others, it's more of an attention thing: designers will focus on the leakage issue. Reducing the leakage current will be their low hanging fruit and that's what they'll go for. Alan

James Awad
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re: Asynchronous DSPs: Low power, high performance
James Awad   5/2/2008 4:08:43 PM
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Hi Alan, Thanks for taking interest in this topic. You are correct, whether you use synchronous or asynchronous logic, this does not change the leakage characteristics of the underlying gate technology. Take note however that ASIC designers have different kinds of gates at their disposal. Semiconductor foundries offer different processes within a given geometry. For example, a foundry may offer HVT, SVT and LVT gates, offering different voltage thresholds in exchange for better or worse leakage characteristics. Therefore, if your product is battery operated and needs to save power when in stand-by, you will tend to use low-leakage, slower gates. If your product is typically always active, you can in fact reduce total power by using higher-leakage gates, since they will consume less "active" power when in operation (which is most or all of the time!) For more information on how to optimize a design for power, you can take a look at another article we've published on the subject: http://www.dspdesignline.com/187200450. It discusses the topic of leakage current in detail. As a side note, Kenton referred us to a general Wikipedia article on asynchronous logic. Don't forget that there are many approaches to asynchronous logic. The approach mentioned in the wiki, which Octasic does not employ, is to encode the timing (clock) into the data itself. As the Wiki mentions this can create larger area in some circumstances than the equivalent synchronous circuit.

AlanLevi
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re: Asynchronous DSPs: Low power, high performance
AlanLevi   5/1/2008 3:56:02 PM
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Isn't it true that clocked and asynchronous logic suffer equally from increased leakage current at shrinking geometries?

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