This series is excerpted from "RF and Digital Signal Processing for Software-Defined Radio." Order this book today at www.elsevierdirect.com or by calling 1-800-545-2522 and receive an additional 20% discount and free shipping. Use promotion code 94446 when ordering. Valid only in North America.
Part 2 looks at sampling for band-pass signals.
Part 4 examines the peak to average power ratio (PAPR).
7.3 The AGC Algorithm
The purpose of the automatic gain control (AGC) algorithm is to regulate the received signal strength at the input of the ADCs such that the required signal SNR for proper decoding is met. For example, if the received signal strength is weak at the antenna, the AGC algorithm boosts the receiver gain stages in order to minimize the noise and bring the signal level to an acceptable SNR. Likewise, if the received signal strength is strong, the AGC algorithm attenuates the receiver gain stages in order to avoid signal clipping and nonlinear degradations that would otherwise deteriorate the signal SNR. In receivers that employ modern digital modulation techniques, the AGC corrects for long term fading effects due to shadowing. The short term fast fades, especially those denoted as frequency selective fades, are corrected for in the digital equalizer, be it a RAKE receiver, a decision feedback equalizer (DFE), or any other form of equalization designed to deal with this type of fading. After equalization, any remaining symbols in error are corrected, or attempted to be corrected, in the forward error correction block using a variety of appropriate coding schemes. It is important to note that the AGC must not correct for fast fades especially within a data slot, or a block of symbols within frame. Performing amplitude gain control within a coherent block of data could serve to adversely affect the equalizer or forward error correction.
The AGC loop mostly controls various analog gain and attenuation blocks at various points in the receive chain. For example, in a superheterodyne receiver, depicted in Figure 7.8, the AGC loop could switch the LNA gain from low-setting to high setting and vice versa, perform a similar function concerning the post mixer amplifier (PMA), and vary the gain of the voltage gain amplifier (VGA) to maintain a certain signal level relative to the noise in the receiver thus maintaining an acceptable SNR. The object of this discussion is not how to control the receiver line-up, but rather how to design the digital loop that estimates the input signal power and adjusts the gain accordingly to maintain a satisfactory SNR. The following analysis is applicable to most common receiver line-up architectures.
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Figure 7-8. Block diagram of superheterodyne receiver.
7.3.1 The Loop Detector
The first order AGC loop is depicted in Figure 7.9. The analog in-phase and quadrature input signals I(t) and Q(t) undergo amplifications or attenuation by the in-phase and quadrature VGAs as well as the LNA and PMA gain stages. At the output of the ADCs the discrete in-phase and quadrature signals are then squared and added to generate the instantaneous signal power:
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Figure 7-9. The AGC loop.
The instantaneous output power provided in (7.43) is obtained at the output of the detector. Most practical detectors, however, implement an approximation to (7.45) or its square root in order to simplify the digital ASIC implementation. The most common approximation takes the form:
The most commonly used approximation of the envelope based on (7.46) is:
Other approximation examples include:
In order to evaluate the performance of the various detectors of the form presented in (7.46), it is instructive to compare their performance with the exact detector presented in (7.45). To do so, let us compare the amplitude of (7.46) to the unity vector at the output of the exact detector, resulting from I(n) = cos(?) and Q(n) = sin(?). That is, compare the magnitude of (7.46) to 1 for various phase angles ?. The result of these comparisons is depicted in Figure 7.10. However, regardless of the detector used, its performance largely depends on the input data. For random white noise type input data, the performance of the AGC with an estimated detector approaches the performance of an AGC with an exact detector at the cost of reducing the attack and decay time resulting from reducing the gain value at the input of the loop filter.
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Figure 7-10. Performance of various AGC detectors based on (7.46).
In the ensuing analysis, only the true instantaneous power estimate based on (7.45) will be used. The output signals to the ADCs must not undergo any digital channel filtering before detecting the instantaneous output power in order to provide a true estimate of the signal power. This is essential, since a channel filter attenuates the interference or blocker and prevents the AGC from reacting properly to it. Certain AGC designs, however, rely on two instantaneous power estimates: one before the digital channel filters, which approximates the signal plus blocker power, and one estimate after the digital channel filters, which estimates the desired signal power without the effect of interference and blocking. In this discussion, we will limit our analysis to the case where the signal plus interference instantaneous power is used to perform gain control.