The Viterbi algorithm (VA) is a common means for error correction in digital communications. Due to its strength, it is applied to most digital communications standards today.
In this article we demonstrate how to implement a punctured rate 1:4 (effectively 1:3) Viterbi decoder. Using the specialized instructions of the Blackfin processor, we reduce the cycle count of the Forward Path to 26 cycle/bit. Then, with a careful selection of the data structure used for the Traceback, we implement this section in a cycle count of about 4 cycles/bit.
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