With silicon rapidly evolving from single-function devices to more intricate systems on chip (SoCs) that pack myriad functions on just one die, designers are facing unprecedented levels of complexity.
Improvements in process technology continue to push the theoretical limits of wiring to create crosstalk bedlam. The need to integrate existing or third-party intellectual property (IP) offer unusual challenges to teams accustomed to building chips from scratch. And, design tools and methods often solve yesterday's problems better than current ones.
A solution, for both the silicon and design tools challenge, has fortunately arrived from an unlikely space: The makers of large FPGAs tailor-made for a wide range of SoC applications.
For example, an increasing number of wireless and commercial applications are well served by FPGAs with geometries of 0.13 micron with multi-million gates and operational frequency ranges of up to 400 MHz. A bonus: The re-programmability of FPGAs is particularly useful when designing to rapidly evolving wireless standards.
As the size and complexity of FPGAs have grownin fact, their geometries are shrinking faster than application specific integrated circuits (ASICs)so have design challenges. FPGA designers are learning, just as their ASIC counterparts did a few years back, that existing design tools and methodologies for floorplanning, static timing analysis, IP design and reuse, and teamwork design are inadequate.
New approaches, relying on integrated floorplanning and analysis to slash design convergence times and improve quality of results in these SoC-scale FPGAs are now appearing just as they have in the ASIC world. These allow designers to break FPGAs into smaller blocks to tackle interconnect delay and associated place and route problems, and project teams can more easily tackle individual areas of the chip as they do with ASICs.
With these tools, FPGA-based SoC project teams have the ability to practice design reuse or even import third-party IP for individual portions of the design. This also gives them a better handle on physical block characteristics such as utilization, congestion, and power consumption earlier in the process.
Today's most complex FPGA designs often frequently require 50 or more iterations through a conventional physical implementation flow due to unforeseen routing congestion and timing issues. However, floorplanning with analysis capabilities can effectively overcome these design convergence issues, helping to meet design goals quickly and predictably by minimizing the number and length of place and route iterations.
New software products, such as the PlanAhead hierarchical design and analysis tools from Hier Design, provide an ASIC-style methodology for multi-million gate, ultra deep submicron FPGAs. Tools such as this enable designers to partition the physical design into smaller, manageable pieces, reducing the time to design, verify, and implement the design. Partitioning also provides an incremental design methodology for faster engineering change orders (ECOs), not to mention reducing place and route run times and computational resources.
Designers can achieve circuit performance improvements by applying design planning techniques and analyzing the results of their planning early in the design process. Connectivity analysis shows the designer how to create a higher performance floorplan, while utilization analysis assists with logic design and device selection. This results in the ability to reach physical design goals faster with less iteration.
The key to optimal floorplanning is intuitive visual feedback. A good floorplanner should clearly show all available device resources including logic instances, RAM, multipliers, clock regions, I/O, and the interconnectivity of those resources. Proper resource analysis and visualization software makes it intuitively obvious how to guide placement and alleviate congestion. As designers place and modify objects, the software automatically assigns and maintains the corresponding placement constraints.
During logic design, the designer does not always know the best way to partition the design for maximum performance. As the design implementation starts to take shape, and the designer can see where congestion and lengthy routes are occurring, a good floorplanner enables the logical and physical hierarchies to diverge. For instance, a designer should be able to grab all of the logic within a critical path, regardless of where it is in the logical hierarchy, and constrain it such that it is always placed tightly together in a given block. This ensures minimal routing distance, and delay, for this critical path. The floorplanner should also be able to keep track of hierarchical changes so that subsequent ECOs do not force you to redo all of your work, breaking the design flow.
Leading-edge FPGA designers are now encountering problems that were once limited to ASIC designers. Interconnect delay is dominating the design performance. Project teams serious about reducing the cycle time and reaching their performance goals have begun to adopt well-tested and well-proven methodologies found in ASIC design. These new methodologies are enabling project teams to reduce the number of hardware iterations, an all-important time-to-market consideration for SoCs.
About the Author
Dino Caporossi is Hier Design's Vice President of Marketing in Santa Clara, CA. His email address is email@example.com