Advances in process technology are enabling a profound increase in the number of commercial applications for field programmable gate arrays (FPGAs). Technology breakthroughs from 10-million gate density to 400 MHz clock speeds and 300 mm wafer sizes have made them readily affordable for volume production.
FPGA gate counts have dramatically increased and prices have fallen, whereas application specific integrated circuit (ASIC) design and manufacturing costs per gate continue to climb. Unless speed or power usage is particularly critical or production volumes high, it is difficult to justify the expense of ASICs.
Due to the increasing number of gates in high-end FPGAs, design problems once limited to ASICs are now beginning to surface. FPGAs have grown so large and complex that designers are encountering the same kinds of convergence problems, obstructing or even preventing design completion.
Interconnect delay is a serious concern, for example. As witnessed when high gate-count deep submicron ASIC designs first emerged, interconnect can account for as much as 70-90% of overall circuit delay as dimensions shrink below 0.18 µm. These large design sizes also impact cycle time due to software runtimes and an increased number of performance-based iterations.
Other types of problems include slow or unpredictable routing results, routing congestion, tightly packed designs, clock complexity, critical paths spanning hierarchy, and the inability to maintain design performance.
Traditional Electronic Design Automation (EDA) software, developed before deep submicron technologies, higher gate counts and interconnect delays, has failed to keep pace with the growing complexity. This forces designers to fix each problem individually and then re-implement the entire flattened design. The result is lengthy and numerous design iterations that can lead to cost overruns, slipped schedules and missed market opportunities.
In the traditional EDA flow, designers synthesize register transfer level (RTL) code using coarse interconnect estimates and then design implementation tools map, place and route the synthesized netlist. If the design fails to meet performance constraints, the designer makes changes to the RTL and/or constraints and then iterates the design throughout the flow.
As a result, FPGA designers face lengthy, flat place and route runs. Each run uses random seeding, which produces unpredictable results, so it can take many such runs to reach closure. Unfortunately, even a routine, minor logic change breaks this process, necessitating another lengthy set of flat place and route runs to regain design closure.
ASIC design has been improved through the use of hierarchical floorplanning, a design step between synthesis and place and route that reduces the number and length of design iterations. FPGA designers serious about reducing the cycle time and reaching performance goals are adopting these ASIC-style techniques, enabling them to address complex issues at the point of maximum impact.
Figure 1: An ASIC-style methodology shortens and reduces the number of design iterations between logic synthesis and place and route
An ASIC-style design methodology provides designers early analysis and planning of their designs to maximize performance and avoid lengthy and repeated iterations. It also provides powerful incremental and modular design capabilities to accommodate routine design changes and ease intellectual property (IP) reuse across multiple designs.
An ASIC-style methodology provides a representation of the final design early in the design cycle to avoid potential implementation problems. This gives designers intuitive feedback so they can quickly visualize and correct problems such as routing congestion before they occur. Designers can rearrange blocks or physical hierarchy to lessen congestion and reduce lengthy interconnect, attaining higher performance. Such a methodology also reduces overall place and route time and shortens routine design changes or engineering change orders (ECOs).
To implement an ASIC-style methodology, the designer starts by creating physical hierarchy for the major blocks of logic. An advantage to creating hierarchical blocks and not flattening the design is faster ECO time. When design changes are necessary, the iteration time is short and the overall timing of the chip remains relatively stable. The designer only needs to do a quick place and route of blocks that were changed.
Some blocks are more timing-critical than others. The designer can determine this by running static timing analysis on the design, prior to place and route. The timing report shows which blocks of the design may not meet timing requirements.
The report also differentiates whether timing problems are due to long logic chains or interconnect delay. The designer can modify the floorplan to fix problems related to interconnect delay, or re-synthesize to fix logic-related timing problems. Connectivity analysis displayed on the floorplan also shows interconnect density between logic blocks, identifying potential areas of routing congestion.
Figure 2: Static timing analysis can identify and highlight critical paths in the design so floorplans can be adjusted to avoid timing problems
With an ASIC-style methodology, designers can manipulate the physical hierarchy independent of the logical hierarchy. Often this is necessary to maximize performance, utilization or other design goals. To alleviate timing problems, the designer can modify the floorplan by rearranging or repartitioning the blocks.
After place and route, the designer can tweak the design to fix any remaining timing problems. Using the schematic view as a guide, the designer can select critical path logic and place it into a small block, eliminating the timing problem by minimizing interconnect distance. Alternatively, the designer could simply move critical path logic within the floorplan view to shorten interconnect distance.
An ASIC-style methodology also encourages a team approach. While a typical FPGA design is implemented in a single-user flow, the ASIC-style methodology enables a block-based, multi-user approacha "divide and conquer" strategy to reduce the place and route time. Or, a designer can change one block while the rest of the design is preserved.
Project teams can more easily tackle individual areas of the chipjust as system-on-chip (SoC) design teams do. This methodology gives them a better handle on physical block characteristics such as utilization, connectivity, and power consumption earlier in the process.
Using IP blocks enables FPGA project teams to quickly follow-up on successful designs in the market with next-generation products since they are not building everything from scratch each time.
FPGA complexity has grown large enough to serve a broad base of applications. Unfortunately, this added complexity has brought with it a large number of familiar problems formerly associated with ASIC design. Adopting an ASIC-style methodology alleviates these problems, enabling designers to more quickly reach and maintain design closure.
About the Author
Salil Raje is Hier Design's Chief Technology Officer (CTO) in Santa Clara, CA. His email address is firstname.lastname@example.org