When the shift from schematic entry and gate-level design gave way to synthesis and register transfer-level (RTL) design expression, the design community settled on two languages: VHDL and Verilog. For a decade, a heated language war ensued with one camp arguing the merits of its language over the other. In the end, both languages won. But in the process, the designer repeatedly asked: "What language is right for me?" With the demands of efficient SoC design, design reuse and IP-based design methodologies, it was clear that the use of both languages simultaneously was required.
But ask any designer if either of these are the only two languages used in practice today, and you will find that it is a truly multi-lingual world filled with C/C++ and dialects of C/C++, Java, Perl, proprietary design and verification languages and more. With the explosion in design complexity, there appears an equal explosion in the use of a supplementary language to complement VHDL and Verilog.
In the case of VHDL and Verilog, the use and application of each of these languages found predominant use based on geography or on the end electronic product being developed. With the convergence of applications into single-chip solutions with global design teams working on them, the drive to accept design units expressed in either language became necessary, if not mandatory. We know VHDL use is greater in Europe and Verilog use is greater in North America. We know telecom companies use more VHDL while microprocessor-based designs are generally done in Verilog. While these are not hard-and-fast facts, they generally hold true. While the cost of VHDL application ownership has been less than Verilog application ownership, we have seen the FPGA design community more likely to embrace VHDL over Verilog. With the reduced need for detailed gate-level descriptions for FPGA designs, FPGA designers did not need to choose one language with support of high-speed gate-level algorithms and RT-level constructs as is found in Verilog. As such, the ability to describe abstract concepts with greater efficiency in VHDL might be a greater factor in the selection of VHDL in FPGA designs over Verilog.
So, what's the best language for you? The chances are you are already using another language with VHDL and Verilog today. The design community continues to show that multi-lingual design solutions are needed.
With advances in semiconductor technology that push design sizes to unimagined heights, your design and verification languages will need to evolve to address your design challenges. Today's language needs to bring together system design, RTL design, verification activities and links into the software development world. But there is no single language that does this. Because of this, multiple languages and interfaces are needed. But, there is hope on the horizon for a solution to these language issuesto unify the use of these multi-language solutions into a small set of languages.
The development of a standard property specification language will help to foster the further development and use of formal verification algorithms that offer property and model checking tools. These tools are not commonly used today. If used at the block level, this technology should be able to prove mathematically the module correctness. The state-of-the-art algorithmic technology in this area does have memory constraints, but when limited to the module level, this problem should be well contained. Beyond opening a new world of verification algorithms, property specification languages will also be used in traditional functional verification environments, since it is possible to translate a subset of a property specification language into simulation monitors and checkers, or what are called assertions. When this can be done automatically for the designer and verification engineer, better feedback on the quality of the testbench will help direct testing of a design to areas of the design which are not being covered as well as other areas of the design.
The third generation of Verilog, known as SystemVerilog, offers designers assertions to support an assertion-based verification methodology as well. Assertion-based design sets the stage for improved synthesis and better verification. Synthesis can infer constraints from assertions and with embedded assertions, superior verification will offer automatic checks that would otherwise be difficult to detect using the Verilog design language itself. The best news is that all this technology will be an evolution of the known and trusted Verilog language.
Assertions will also give a boost to design reuse and IP-based methodologies. It has been rather easy to share design blocks, but design intent was difficult to convey in a design reuse and IP-based design methodology. A designer may have been provided acceptance tests to prove the IP or design block would perform to specification, but there was not assurance that this use of the block was consistent in the target system. Now with embedded assertions, the intent of the designer is automatically part of the IP block. If the IP block was not consistent with a property used in the design, assertion messages of misapplication would be issued when the assertion property is violated. Instead of finding such problems after the production of silicon, designers will be able to detect and correct these problems before the production of silicon.
Are you ready to choose another design language? Well, the question is really rhetorical. The good news is that your trusted design languages and design tools are evolving to keep pace with your design and verification needs. The right design language for you is the one you are using today, since it is evolving to keep pace with your needs.
About the Author
Prior to joining Mentor Graphics in October 1993, Walden Rhines was executive vice president of Texas Instruments' (TI) Semiconductor Group, sharing responsibility for TI's component, consumer products and materials, and controls businesses. He was directly responsible for TI's worldwide semiconductor business. Rhines joined TI in 1972 and held a variety of technical and business management positions, primarily in the Semiconductor Group, but also in the Consumer Products Division, Central Research Laboratories, and Data Systems Group.
Rhines served as chairman of the Semiconductor Technical Advisory Committee of the Department of Commerce, as an executive committee member of the board of directors of the Corporation for Open Systems, as a board member of the Computer and Business Equipment Manufacturers' Association (CBEMA), and a board member of Sematech. He serves on the board of directors of the Electronic Design Automation Consortium (EDAC), and is a board member of both the Oregon Independent College Foundation and Lewis and Clark College.
Rhines holds a BS degree in metallurgical engineering from the University of Michigan, MS and Ph.D. degrees in materials science and engineering from Stanford University, and an MBA from Southern Methodist University. He has also been awarded an Honorary Doctor of Technology degree from Nottingham Trent University.