Decimation Stages with WDFs for Flexible Digital Receivers
Easy adaptation to several mobile communications standards is a design goal for wireless communications transceivers, where end users require low cost, low power, and small device size. We can achieve multistandard capability by moving channel selection into the digital domain, where it can be implemented by programmable digital filters. We need a wideband A/Dconverter in such architectures so that the desired channel is digitized together with the unwanted adjacent channel interferers.
Deltasigma modulators with oversampling are especially well suited for this application because the adjacent channel interferers are filtered out by the decimation stages along with the highpass shaped quantization noise. You don't need additional filtering for channel selection and the antialiasing lowpass filter requirements are relaxed due to oversampling.
For optimal performance, the decimation stages of such a receiver must meet certain requirements, which should be taken into account during the filter design process. You should especially minimize the group delay of the filters to allow the implementation of a fast AGC in the receiver. Furthermore, no significant groupdelay distortion may be introduced in the pass band. To account for the very stringent cost and lowpower requirements in a mobile terminal, you must optimize the decimation filters for a cost effective FPGA or ASICimplementation. Avoid a generalpurpose DSP for multiplications and MACoperations in favor of a lowgatecount implementation. Finally, to account for the required flexibility, the decimation filters should be adjustable with respect to the decimation ratio.
There are several filter structures available for the decimation stages of deltasigmamodulators. This article will show that for the lower decimation stages, properly designed cascade connections of loworder lattice wave digital filters (WDFs) are especially well suited for this application—in particular, with respect to the requirements of a flexible digital receiver. Lattice WDFs consist of a parallel connection of all pass sections. These filters have several advantageous properties, such as lowcoefficient sensitivity in the pass band, low roundoff noise, and an absence of parasitic oscillations. Furthermore, they are minimumphase recursive filters.
A disadvantage, however, is the high sensitivity in the stop band with respect to the coefficients. For high stopband attenuation, you need many bits to represent the coefficient. In order to avoid this problem, the decimation stages proposed in this article are composed of a cascade connection of loworderwave digital subfilters. You can significantly reduce the number of data bits and the number of bits required for the coefficient representation with this method.
Figure 1: Receiver architecture with simple analog preprocessing and flexible digital signal processing
A simple blocking filter processes the RFsignal received at the antenna. The lownoise amplifier (LNA) then preamplifies the signal. The quadrature downconverter in the analog domain performs the downconversion to a low IF or baseband.
The digital part consists of two hardware blocks. The upper digital signal processing module, which operates at higher frequencies, is optimized with respect to chip area and power consumption, but nevertheless offers a certain degree of flexibility by using reconfigurable hardware. The module's main functions are channel selection and decimation. These functions require only a reduced flexibility even for multistandard capability, appropriate for an ASIC/FPGA implementation.
The processor part is used for baseband signal processing and is highly flexible and easy to program. This module can be used for detection, synchronization, equalization, and speech and video processing.
Figure 2 shows the architecture of the digital part of the receive path. Deltasigma modulators digitize the I and Q components of the broadband receive signal after quadrature downconversion in the analog domain. The channel of interest is thus centered around DC. The decimation filters then perform channelselection, together with the suppression of the highpass shaped quantization noise.
Figure 2: Receive path with decimation filters
You can minimize the required hardware for the decimation filters by performing decimation in several stages, with sample rate reduction after each stage. After quantization by the deltasigmamodulators, the signal is digitally filtered by real lowpass filters. The first filter stage performs decimation by a programmable factor M. The following three stages each reduce the sampling rate by a factor of two. You can also bypass each decimation stage so that the decimation ratio is programmable over a large range. Since the decimation stages are designed such that the lowest stage fulfills the most stringent attenuation requirements, you should bypass one or two lower stages such that Stage 2 is bypassed before Stage 3.
Because the uppermost decimation stage is running at the highest clock frequency, you should implement this stage with rather simple filter structures to optimize cost and power consumption. By using cascaded integratorcomb (CIC) filters you can obtain simple hardware structures, which you can implement using only registers and adders. You can avoid the potential drawback of this filter type, severe passband droop, which is dependant on the decimation ratio, by using a modified version of these filters. The socalled sharpened CICfilter (SCIC) requires only slightly more hardware, but shows considerably improved performance in the pass band. The stopband attenuation of the decimation filters is designed to fulfill the attenuation requirements of a fourthorder deltasigmamodulator that requires, in the first stage, a classical fifthorder CIC filter or a comparable SCICfilter.
Filters with a steeper transition band are required for the lower decimation stages. You can obtain a hardwareefficient filter realization with halfband filters, having a symmetrical filter characteristic with respect to F_{s}/4 (F_{s} being the sampling frequency). In this case, 50% of the filter coefficients are zero and must not be implemented. Furthermore, when properly designed, these filters can be clocked with the decimated sampling frequency.
which you can exploit to obtain efficient decimators for sampling rate conversion by two. The number of filter coefficients you must implement is reduced by 50% and you can clock the filter with the lower sampling frequency.
The transfer function of N cascaded loworder bireciprocal lattice wave digital filters is given by
where H_{i0}(z) and H_{i1}(z) are all pass filters. The respective structure is shown in Figure 3. For approximately linear phase, you should design one of the allpass sections in each subfilter as a pure delay.
This decomposition in a cascade connection of loworder wave digital filter sections results in a number of advantages, compared to existing solutions. Bireciprocal WDFs are minimumphase filters that introduce groupdelay distortion. You can obtain a lattice WDF with approximately linear phase in the pass band if one of the allpass subfilters is a pure delay. In the pass band of the filter, the responses of the allpass subfilters must be approximately equal. Since one of the branches is a pure delay, the phase response of the overall filter has approximately a linear phase in the pass band. This will be taken into account by cascading thirdorder cells of bireciprocal lattice wave digital filters, as shown in Figure 3, resulting in a superior groupdelay performance compared to a direct realization of a lattice WDF.
Figure 3: Cascaded loworder wave digital filters
You can get low coefficient sensitivity by cascading loworder sections with high stopband attenuation. Thus, you can represent the optimized coefficients with very simple values and a word length of only a few bits is required. Due to the very simple coefficient representation, no general multiplier is needed, thus minimizing implementation cost. Furthermore, the shorter word length also holds for the signal representation, resulting in reduced implementation cost for the adders and registers. In addition, the cascaded loworder sections are very modular, making it very attractive for VLSIimplementation.
For the application considered, we designed the decimation stages for a minimum stopband attenuation of about 95dB. The strongest requirements hold for the last stage, which can be clocked with the lowest clock frequency. We designed this fourth filter stage for a normalized stopband edge frequency of f_{c}/f_{s}=0.355. For the third decimation stage, you can relax this requirement; however, the discrete coefficient optimization came up with the same filter as for the fourth stage.
Figure 4 shows the architecture of the lattice wave digital filter, designed for use in the third and fourth decimation stages. The decimation stage consists of a cascade of three thirdorder bireciprocal WDF filter blocks, resulting in a total filter order of nine.
Figure 4: Decimation stage consisting of three cascaded thirdorder bireciprocal WDFfilters
We designed the second decimation stage for a minimum stopband attenuation of 80dB from 0.4 to 0.45 and of 95dB from 0.45 to 0.5. You can also implement the filter with the structure in Figure 4, where only two cascaded thirdorder cells are needed, which results in an overall filter order of six.
The optimized values for the three lower decimation stages are listed in Table 1. You can represent nearly all coefficients with only one shiftandadd operation—only one coefficient in Stage 2 requires two shiftandadds.












Table 1: Optimized finiteprecision adaptor coefficients for the cascaded lattice WDFs
By implementing the decimator by 2 with the last filter cell of each decimation stage, you can realize Stage 2 with four registers and 11 shiftandadd operations. You need a word length of only 6 bits for the coefficient representation.
You can realize Stages 3 and 4 with seven registers, 12 adders, and three shiftandadd operations for each stage. For the respective coefficients, you need a word length of only 5 bits. You can also fulfill the attenuation requirements of the fourth decimation stage with a classical ninthorder bireciprocal WDF, requiring four registers, 13 adders, and 12 shiftandadd operations. The word length you need for the coefficient representation is, however, 12 bits. Furthermore, you could also fulfill the attenuation requirements with an FIRfilter of order 23. Compared to classical solutions, you obtain a considerable hardware reduction using the cascaded loworder sections.
Figure 5: Frequency response of the second decimation stage (blue line) and of the third and fourth decimation decimation stages (black line)
The third and fourth filter stages consist of three cascaded thirdorder WDFs. Figure 6 shows the overall frequency response of the three lower decimation stages. A minimum attenuation of 96dB is obtained. When cascaded with the first decimation stage, the minimum attenuation is even higher.
Figure 6: Overall frequency response of the three lower decimation stages implemented with cascaded low order WDFs
Figure 7 shows the excellent passband behavior of the SCICfilter compared to that of a classical CICfilter. The severe passband droop of the CICfilter is avoided. The decimation factor of the SCICfilter is programmed to a value of M=4.
Figure 7: Pass band behavior of the SCICfilter compared to a classical CICfilter
The overall passband behavior of the lower decimation filters is shown in Figure 8. Due to the excellent passband performance of bireciprocal WDFs, the ripple is smaller than 0.05dB. The resolution required for the ADCs of the digital receiver is determined by the dynamic range requirements of the receive path. If the RFfront end is designed properly, you can obtain the required dynamic range from the smallest wanted and the largest unwanted signal, which must be processed in common. You can find the respective values in the physical layer specification of the various wireless and mobile standards as interferer and blocking requirements.
Figure 8: Pass band behavior of the three lower decimation stages with cascaded WDFs
The proposed decimation filter architecture enables the realization of highly optimized but flexible digital receivers. It has been shown in this contribution that you can obtain very effective realizations for the lower decimation stages, by using cascaded loworder wave digital filters. You can implement this filter type with minimum hardware costs compared to other solutions such as classical wave digital filters or FIRfilters. Further advantages of the proposed filter structures are superior sensitivity properties with respect to coefficientquantization effects, better noise performance, and less groupdelay distortion compared to classical structures.