SoC designers place heavy emphasis on tools and techniques that achieve timing convergence between the logical and physical phases of the design. However, correct timing is only one target design parameter. We need more effort put into reaching other design goals, such as power consumption and signal integrity, to achieve complete design closure and signoff prior to committing a design to expensive photomasks.
One of chip design's most often sort-after goals is "timing closure". Simply put, timing closure refers to the ability to synthesize a gate-level representation of a chip from its RTL description, according to a set of timing constraints, and be able to implement the chip's physical representation that will meet those constraints. In the past, this convergence of timing between logic synthesis and a placed-and-routed file was rarely met. After synthesis and gate-level timing verification, a designer would spend a large amount of time creating a physical database for a chip, extract the design from the physical database, and find that it did not achieve expected timing results. Subsequent re-design, re-synthesis, and new layout cost the design project dearly in time and money.
Reaching Timing Closure
The availability of EDA tools that merge aspects of logic synthesis and physical design, along with implementing pre-physical-design timing optimization, has done much to help achieve timing closure and reduce the number of synthesis/place-and-route iterations. Companies such as Cadence Design Systems, Magma Design Automation, Monterey Design Systems, Sapphire Design (now part of Sequence), Silicon Perspective (bought by Cadence), and Synopsys have all contributed to tools that assist chip designers in reaching timing goals. These tools integrate synthesis with physical design, using timing as a constraint.
However, achieving timing closure is only one step towards achieving full Design Closuretiming is only one component of a design's performance specification. Other important design considerations include parameters such as power dissipation (static and active), signal integrity, integration of analog and digital cores on a common chip, and electromagnetic compliance (EMC). Unfortunately, by and large, chip EDA vendors are lagging in efforts to produce tools and tool suites that address these other, important aspects of design closure. Making matters worse, as chip features shrink, SoC designs grow in device count and complexity, and system speeds increase, making all goals of design closure more difficult to realize. Furthermore, programmable-logic EDA tool vendors are further behind in addressing design-closure problems then are ASIC and SoC tool vendors, particularly in optimizing for low power.
After timing, power is the parameter that is most critical for the majority of SoC devices. While designing for timing closure usually also means designing for minimum power, this isn't always true. Alsojust because your chip meets timing requirements, it doesn't mean it meets your power specification as well. This underlines the need for design tools to handle power analysis and optimization, similar to the tools you use to design for timing closure.
Some companies, such as Sequence Design (Power Theatre) and OSC (Orinoco), have already made inroads into what I call design power-closure through power optimization prior to logic synthesisat the design's RTL level or above. Cadence's BuildGates Extreme and PKS also have a partial RTL power optimization capabilitythe tools can suggest portions of a design where gating clocks may reduce power, but do not make any actual changes at the RTL to accomplish the reduction. The tools also do this RTL power-optimization exploration after running static-timing analysis, so that any power optimizations will not interfere with timing. Synopsys' Power Compiler goes a step further by doing automatic clock gating at RTL to reduce power. Several EDA companies have tools that do power analysis and optimization at the gate or transistor levels, but this is too late in the design cycle to be useful without prior RTL or higher-level power analysis.
Reaching design closure when including signal-integrity (SI) effectsSI closureis difficult. An initial problem is that many static-timing-analysis tools, embedded in tools that help achieve timing closure through the integration of synthesis/optimization/physical-design tools, do not take crosstalk between wires into account when calculating timing delays. The crosstalk, which is accentuated by shrinking processes and faster on-chip clocks, is due to simultaneous switching of neighboring wires (and can extend beyond "nearest neighbor" interconnects).
By distorting signal waveforms, crosstalk can result in delay variations not just between a driver and receiver, but throughout a particularly sensitive net on a chip. An aggressor wire switching at the same time as a victim, but with a signal moving in the opposite direction, results in increased delay in the victim. This scenario may result in a potential setup failure in a latch driven by the victim's driver. If the aggressor's signal moves in the same direction as a simultaneously switching victim, you can get a decrease in delay time, which causes a potential hold failure in a following latch. Complicating the situation is that crosstalk-induced timing variationsincreases or decreasesare dependent on the slew rates of the victim's and aggressor's signals. The bottom lineSI closure is much more difficult to achieve than timing closure with current design tools, but is becoming a critical component in achieving silicon success (for a good discussion of signal-integrity effects, see Signal Integrity Sign-Off Verification).
Some EDA tools address SI issues during timing optimization, but are only partially successful in eliminating SI problems prior to physical implementation. Along with crosstalk, you still need to consider other SI problems such as voltage droop, ground bounce, and electromigration. Designers still need to check SI after placement and routing, and often need to modify the physical layout to meet SI specifications.
What About EMC?
At this time, chips are not usually designed to meet EMC specifications. Such specs are just not in place for chip designs; instead, the people who design the boards and boxes in which these chips are embedded have the EMC headache. That's a shame, since a digital chip running at hundreds of MHz makes a dandy little broadband radio transmitter when PCB traces are connected to its outputs. Modified versions of board-level EMC-analysis tools, such as the former HyperLynx tools (recently brought into Mentor Graphics as part of their Innoveda acquisition), would be useful to have during chip design to reduce a chip's electromagnetic interference (EMI) prior to being placed on a printed-circuit board. However, if I'm a chip vendor, since EMC is not part of a chip's specification, why design for it since it costs more money and takes time away from other design activities?
What's Needed to Get the Job Done?
At this time, designers have a variety of tools to help them reach timing closure with their chip designs. However, EDA tool vendors need to put more effort into providing tools and methodologies for optimizing designs at higher levels of design abstraction to meet power and SI specifications. In fact, Gary Smith, Dataquest EDA analyst, thinks that timing is not the primarily concern of "bleeding edge" chip designers, it's power. OK, EDA vendors, step up to the plate!