Yield ramp has historically been the fab's burden. The yield ramp cycle was cleanly partitioned into three phases: process development, pilot production and volume production (Fig. 1).
1. Industry has traditionally partitioned process development and yield improvement into three phases.
Designers slept well when using a process qualified for production, knowing that as long as their designs obeyed the rules, good yields would result.
With today's sub-100nm process technologies, the fab too often discovers that parametric and systematic yield issues creep into volume production. We contend that lower yields, due to systematic and parametric failures, are no longer just the fab's problem. These failures often occur because complex topologies, created by designers, were not envisioned or adequately characterized during process development.
The fab is attempting to address such yield fallout through more complex design rules and guidelines that will hopefully capture the variety of clever layout choices designers may make. But the effective application of more complex rules and guidelines requires more sophisticated analysis tools not yet available. Lacking such tools, the fab may opt to mitigate the emergence of new yield limiting mechanisms by imposing greater restrictions on the choices that designers can make (e.g. by allowing only one poly gate orientation, or by forbidding certain via cluster configurations). Such restrictions may create area penalties that dilute the benefits of adopting the new process technology.
A framework that allows manufacturers and designers to work together in a collaborative fashion is critically needed to address these new process-design interactions. Such a framework must first supply characterization solutions for obtaining the data necessary for both process and design yield improvement. This paper describes a solution to this challenge.
Practical and effective parametric characterization
Achieving practical and effective parametric process characterization in the sub-100nm domain poses a number of challenges, not the least of which are:
- A critical need for a greater density of test structures on the test mask which support fine analog measurement resolution.
- Measurement of device parametric variability within-die (not just die-to-die, wafer-to-wafer, and lot-to-lot).
- Measurement of device parametric variability over a greater number of device contexts and topologies.
- Lower test time per test structure
- A characterization solution extensible across the process life cycle.
Traditional process characterization (wafer probe) methods using discrete test structures and memory arrays cannot adequately meet these requirements (for reasons we will elaborate on below). We describe here an innovative approach that is complementary to discrete structures and dense bitcell arrays and which meets the above challenges.
The parametric ActiveMatrix approach
The term Parametric ActiveMatrix ("PAM") is coined to refer to a circuit, similar to a memory array in that it employs an addressable, cell-based architecture, but innovative in that it enables high resolution analog measurements not possible with memory arrays. Each PAM cell contains any one of a wide variety of test structure types and sizes (Fig. 2). Many of the same discrete test structures utilized in conventional testchips can be incorporated into the PAM platform. Thus, this architecture combines the density improvement of cellular arrays with the measurement resolution obtainable with discrete test structures.
2. The Parametric ActiveMatrix enables high resolution analog measurements.
With the PAM, sets of test devices are conveniently designed and grouped to fulfill learning objectives such as design rule optimization, device IV characterization, device mismatch characterization, OPC model verification, etc. Conventional test structure elements (sometimes referred to as 'test element groups,' or TEGs) require far greater silicon area to achieve similar sets of experiments. The sections below describe how the Parametric ActiveMatrix approach meets the aforementioned challenges to effective parametric process characterization.
Greater parametric test structure density
Discrete test structures consume large amounts of silicon area, primarily due to the large pads needed to individually probe these structures (Fig. 3). The geometric increase in the number of design rules and (hence) test structures required with each new technology generation has made it prohibitively expensive to continue this conventional approach. In addition, a larger set of parameters must be monitored as the process goes into production.
3. Pad requirements with conventional and Parametric ActiveMatrix approaches differ considerably.
This creates a difficult problem since the available scribeline space does not increase with each process technology generation. In fact, it has been steadily reduced as scribeline widths have shrunk from 100um to 80um and today even to 50um. In both technology development and production scribelines, the PAM platform reduces test structure area requirements dramatically, providing a much-needed solution.
As an example, considering a square pad size of 70um on a 130um pitch, 1000 parametric test structures would consume approximately 35 mm2 of area using conventional methods. With the PAM platform, a single pad frame consisting of about 20 pads can accommodate over 1000 devices for full analog test and consume only about 4.3 mm2 of area. Often, smaller cell sizes can be used to further reduce area.
The PAM supports a full Kelvin (force/sense) measurement on each terminal of the test device within a cell. Consequently, the analog measurement resolution is compatible with that of the most accurate discrete test structures. In fact, the only types of tests done with discrete structures that are not supported by the PAM are those requiring significant current or voltage overstress, or applied voltages below wafer ground.
Careful design techniques need to be employed to ensure that the leakage floor of the PAM platform is suitably low, and that the circuit is robust against wide excursions of process parameters commonly encountered in the early stages of process development. Circuit parasitics of the array that may impact measurement accuracy must also be properly handled.
Figure 4 summarizes the area efficiency and measurement resolution of discrete test structures, SRAM/ROM's and the active matrix platform technology for comparison. SRAM and ROM types of memory arrays offer the lowest area per test device. Though these circuits typically provide only a pass or fail (i.e. binary) signature, the fab is able to use them to quantify the probability of functional failures occurring due to random and systematic defects down to part-per-million levels. The PAM fills the increasingly important need for obtaining statistics of analog quantities within-die.
4. The graph compares parametric resolution and density.