Tackling Power Integrity in FPGA Custom Designs
The tools and flows available to support power integrity analysis in the context of an ASIC development flow are well defined and proven. However, designs such as advanced FPGA devices that are typically implemented using a full-custom approach in latest process technology supporting wirebond or flipchip packaging, pose some significant challenges that warrant special attention and flow modifications. For example, a one billion-transistor custom design with a die size in excess of 20mm per side has specific requirements that constrain the type of analysis that is possible. These requirements must be satisfied and used to drive the overall analysis approach.
Full-custom FPGA designs typically have a small number of different block types, many identical block instances are replicated within the design. Abutment enables connectivity between the blocks. This means that the power network is very complex, with approximately 600 power pins per block, and some blocks using more than 6000 power pins. This level of complexity places demands on the capabilities of the analysis tools far beyond most ASIC design projects.
Typically, design teams do not have access to unlimited compute resources, thus the ability to perform analysis within a reasonable run time using high-end, yet standard computers is essential. The ability to model a one billion transistor design in the main memory of a 64-bit machine (supporting 60 GB of memory) supports this goal. Typically, design teams want to validate the results within 12 hours or less. Fast turnaround time for incremental changes is also an important benefit.
The second key requirement is accuracy. In general, designers will have established an acceptable error margin, comparing the analysis output with the silicon. A typical target is achieving results from the voltage drop analysis that are within 10% of the measured silicon.
The full-custom nature of the design means that there are no standard cells and the models required to support voltage drop analysis with the analysis tool have to be generated separately. However, the objective of any design flow is ease of adoption and use. In general, any modeling conducted within the context of a custom design should also provide a simple representation of complex behavior that enables faster analysis.
Model Support in Rail Analysis Applications
Rail analysis tools that support ASIC as well as FPGA full-custom designs support various, flexible modeling approaches (Figure 2).
- White Box Model
This approach models the entire connectivity of the power network in a block, while providing voltage drop results on every node inside the block. Because of this, white box models are preferred for sign-off purposes. However, the size of the network is directly proportional to the complexity of the power network of the block. In general, white box models require more memory than other modeling approaches in exchange for higher accuracy and the ability to calculate voltage drop/EM at any point of the design.
- Gray Box Model
Gray box model describes the behavior of block power grid with transconductance, i.e., the resistance between its ports and currents at the ports. It is an equivalent circuit representation of the white box model that enables rail analysis to be performed at the same level of accuracy for the power grid where it is employed. The size of the model increases quadratically with the number of ports, therefore if used intelligently, it provides a smaller matrix size. A gray box has the drawback of only calculating voltage drop/EM at its ports.
2 White and Gray Box Modeling offer accuracy Vs capacity
Overall, white box modeling provides higher accuracy while gray box models reduce the memory consumption for voltage analysis. Given the characteristics of an FPGA design, the key question remains, which modeling approach is best suited to a billion-transistor power network analysis? The answer depends on the characteristics of the design and the analysis trade-offs.
A flat full-chip analysis using white box modeling requires much more computer memory to perform a power integrity analysis. For example, a full-chip analysis of a one billion transistor design requires approximately 300 GB of main memory. The favored strategy would be using a hierarchical approach with gray box models for improved memory efficiency.
However, billion transistor full-custom designs may contain a huge number of ports, which can also impact the memory required for gray box modeling. Consequently, further modeling optimization may be required to manage the memory consumption. Advanced rail analysis tools use specific data reduction techniques for various applications to decrease memory demands while delivering high accuracy. A similar memory reduction technique for FPGA designs is outlined below.