Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
This method simultaneously optimizes the number and positions of sleep transistors and the power network's grids and wires for minimum area, maximum routeability with a given IR-drop target. With this automated method for synthesizing the power network, you can more easily take advantage of power gating to reduce leakage power consumption dramatically in SoCs.
Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. (These sleep transistors can also be NMOS footer switches.) Inserting the sleep transistors splits the chip's power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off.
The quality of this complex power network is critical to the success of a power-gating design. Two of the most critical parameters are the IR-drop and the penalties in silicon area and routing resources. Adding 10 percent to the design's silicon area for the switch cells could result in a less competitive product or even failure in the market. . Overly conservative power routings would make a chip unroutable in a sub-90nm power-gating design where routing congestion issues are often observed.
Power gating can be implemented using cell- or cluster-based approaches or a distributed coarse-grained approach. Adding a sleep transistor to every cell that you want to turn off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issues introduced by inter-cluster voltage variation that are difficult to resolve. The coarse-grained approach implements the grid style sleep transistors which drives cells locally through shared virtual power networks (Figure 1). This approach is less sensitive to power/voltage/temperature (PVT) variation, introduces less IR-drop variation, and imposes a smaller area overhead than the cell- or cluster-based implementations. The method described in this article uses the coarse-grained approach.
1. The coarse-grained approach implements the grid style sleep transistors.
The fake-via method
To achieve simultaneous optimization of the number and position of sleep transistors as well as the power network, a fake-via method is introduced to model the channel resistance of a conducting sleep transistor as well as the transistor's placement and physical connections in the synthesis of a distributed coarse-grained power-gating network. Compared to a custom-designed, script-based implementation method used in many power-gating designs, the new method has produced significantly better sleep transistor power/ground networks with 65 percent reduction in sleep transistor area and an average 14 percent IR-drop reduction.
Figure 2 shows the resistances involved in the permanent VDD network (labeled VDD), the virtual VDD (VVDD) network, and the sleep transistors (modeled as vias: Rvia). As seen in Figure 2 the network branch resistance Rwire depends on the branch segment's length, width and thickness:
Rwire = ρ * ls / ws
where ls and ws are the length and the width of a branch segment of the network, respectively, and ρ is the sheet resistance per square.
2. The network branch resistance depends on the branch segment's length, width and thickness.
The current sources at the VVDD network nodes represent the worst-case current of the cells connected to the nodes. The fake via's resistance is the channel resistance of a conducting sleep transistor whose drain and source are biased at the defined sleep transistor IR drop target. Simulations of the sleep transistor channel resistance across different Vds bias points show that the resistance is not sensitive to Vds, so a constant resistance value provides a fairly accurate model.
To calculate the necessary voltage and current values for the network, you can use nodal analysis (NA) or modified nodal analysis (MNA) to find values for the equation:
Gx = b (Eq. 1)
where G is the conductance of the matrix, x is the vector of voltages at the nodes, and b is the vector containing the current signatures of the cells at the nodes. Solving this equation gives the voltage at each node in the power network. With the node voltages, you can calculate node IR drops and branch current density.