Most power supply and system power delivery designers today are intimately familiar with concepts of power network impedance, bypass or decoupling capacitor frequency responses, and important roles played by device electrical aspects such as effective series resistance and loop inductance. As entire systems are integrated onto silicon chips, these system-level, frequency domain, 'analog' design and verification aspects are becoming increasingly important, particularly in nanoscale SoC design. Power Integrity analysis in SoC's is hence moving from traditional IR Drop to total power integrity, and true-electromagnetic simulations, comprehending all aspects of interactions between integrated circuit blocks and the common power delivery network. This article sheds light on key differences such as voltage droops and noise wave propagation resulting from on-chip load interaction with power network impedance and discusses how total power integrity may be rigorously inspected through rapid analyses and physics-based simulations with corresponding benefits to SoC cost and time-to-market/money.
What is Total Power Integrity?
In brief, power integrity (TPI) is comprehensive, true-electromagnetic analysis of interactions between load circuits in a SoC/SiP with power distribution network partitions and delivery system that provides a spatial and temporal view of the degradation of the ideal nature of power supply voltage provided.
The EDA industry enabling Ultra Large Scale Integration (ULSI) design has been moving towards TPI, albeit slowly. Traditional IR Drop investigations are augmented by 'Dynamic IR Drop' in recent years, employing intra-cycle load current profiles (current spikes at clock edges, in other words) in order to isolate 'peak-noise' values rather than just the multiplied product of an average current and power path resistance. The availability of intra-cycle current profiles enables a move to total power integrity investigation that includes all electromagnetic aspects of the interaction of load currents with power network attributes. In TPI analysis, the impedance of a power network is fully represented in addition to power path resistances, providing a complete picture of the response of the network to excitation stimuli such as load currents.
Power distribution network Impedance and Voltage Droops
A lossy transmission line is often represented by its characteristic impedance as
In a nanoscale SoC, the power distribution network and integrated circuits can be abstracted into similar characteristic impedance, with resistance and inductance of power bus wires forming R, L respectively, and leakage conductance of distributed semiconductor devices as well as their intrinsic capacitance forming G and C. Given that leakage is highly non-linear with voltage, a simpler model without G is more useful in understanding the behavior of a power network to stimuli changing network node voltages. This model considers the resistance and inductance of power bus wires and a distributed capacitance corresponding to the density of integrated semiconductor devices. When excited by a step current source, the transient response of such a network is given by:
where Vi is the initial voltage, ΔIis the current step, Lp is the effective loop inductance of the power path, Cd is the distributed capacitance,
is the natural oscillation frequency,
is the damping factor, with rs being the effective series resistance in the power path.
There are two distinct parts to the time-domain response of the power network to a change in stimulus. One is the 'transient' first part that contains a damped sinusoidal response, and the other is a 'static' or DC response. In a more complex power network, the transient part may contain multiple sinusoidal responses at different natural frequencies corresponding to distinct filter stages in the network.
The static portion of the response is what traditional IR Drop tools evaluate. Under the assumption that power bus resistance is by far the dominant impedance encountered by supply currents, traditional IR Drop analysis suffices to determine voltage variation in different portions of the power network. With the inclusion of peak instantaneous currents into the analysis in 'Dynamic IR Drop', maximum noise values are also inspected with some accuracy.
But this assumption that resistance and resistive voltage drops dominate breaks down for wide, low-resistance, global power distribution in a SoC, where resistance tends to be a small component, and loop inductance tends to dominate given the sparseness of the distribution network. In this scenario, voltage variation in the power supply is a combination of both transient and static aspects of response to a stimulus, with transient behavior seen primarily in wide, low-resistance buses, and static drop seen in high-resistance, low-inductance, and dense low-level interconnect. This behavior leads to a partitioning of SoC power distribution networks, where both static and true-dynamic (transient) analyses are necessary, and the possibility of optimization of metal usage between the two partitions ensuring lowest overall voltage variation. The maximum amplitude of transient voltage droop response is given by:
Which represents dynamic voltage droop. Given that transient response is a sinusoidal superimposed variation, a corresponding overshoot also manifests, which may affect reliability and lifetime of integrated semiconductor devices. Inclusion of dynamic voltage droops, overshoots and noise propagation provides total power integrity; these aspects of power network behavior are distinctly absent in IR Drop analysis.
The quantity represents approximate power distribution network impedance that determines dynamic voltage droop. This impedance may be diminished in any region of a SoC by appropriate addition to capacitance, or reduction in inductance through power bus and distribution architecture, thus reducing voltage droops and enhancing total power integrity. But such reduction in noise has a distinct impact on the temporal nature of noise propagation as will be shown further.
Dynamic Voltage Droop: getting better, or worse?
A simple derivation to understand the progression of dynamic voltage droops with scaling is helpful to recognizing a critical need for total power integrity verification in nanoscale USLI design.
Consider a Roots of Two Scaling scenario:
- Capacitance-per-unit-area, Ca, scales by , operating voltage scales by , frequency scales by , and chip area scales by .
Following this constant-power scaling direction, and inspecting the change in Dynamic Voltage Droop in a unit area (/ua) of integrated silicon, we get:
- Since C/ua scales by , and voltage scales by , ΔI scales by
- Assuming the effective L/ua doesn't change, reduces by a factor of .
in the scaled process generation, the dynamic voltage droop amplitude:
, or by a factor of
for constant power scaling.
Note that this droop trend calculation is based upon filter step responses that are independent of the operating frequency, and is different from discrete L*di/dt noise calculations , because it considers the droop absorbing impact of distributed capacitance, and calculates droops over unit silicon area. Nevertheless, it is clear that transient voltage droops are increasing at least by the inverse of the process scaling factor in constant-power scaled designs. Additionally, per unit area, ΔI * r drop increases by * , assuming effective resistance does not change in the scaled process, which is not true since higher frequency currents tend to crowd within low-inductance pathways and thus do not take advantage of full metal widths of the power bus wires.
Some engineering directions stand out from these trend studies:
- employ total power integrity investigations for nanoscale ULSI chips,
- minimize power bus loop inductance values,
- optimize and balance metal usage between global and local power distributions in SoC's, and
- address second order effects stemming from high-frequency currents induced by faster switching edge-rates in nanoscale processes: don't let skin effect become an unanticipated issue.