Circuit design implementation has become progressively complex in deep submicron technologies. Multiple processor cores, I/Os, several types of memories, complex analog circuits, and synthesized logic are being designed onto the same chip. Advanced IP integration proficiencies are needed to realize today's complex systems-on-chip designs and to keep up with the high demand in the communications semiconductor market. Ensuring product reliability to meet design goals and to achieve good yield is of significant and continuous concern.
The electronic design automation (EDA) industry has provided physical verification tools to cover the growing requirements for physical implementation of circuit designs. Design rule checking and layout versus schematic verification processes have been evolving tremendously to be able to verify the increasing complexity of design rules and advanced device parameters extraction. But with complex IP, system integration, and multiple power domains, greater flexibility and power to handle emerging circuit verification demands are needed in the EDA tools available today.
The Challenge of Checking Electrical Rules
Electrical rule checking (ERC) is a methodology used to check the robustness of a design both at schematic and layout levels against various "electronic design rules". These design rules are often project-specific and developed based on knowledge from previous tapeouts or in anticipation of potential new failures. Not complying with these rules can result in reduced yield, defect escapes to customers, and delayed failures in the field -- without a doubt, design robustness is compromised when ERC is not enforced.
Traditional approaches to electrical rule checking may involve circuit simulation or fault analysis, it may be done according to guidelines that were developed as a part of a design review process, or it may be completely overlooked. Simulation or manual checking can start to break down with increasing design sizes and layout dependency-related issues. Simulators may have difficulty handling large designs, and the chances of missing errors during manual checking increases as the complexity of a design increases.
Conventional ERC includes checking floating devices, floating nets, floating pins, connecting high voltage to thin gates, and maximum allowed series pass gates, etc. Similarly at the layout level, several checks may be performed such as net area ratio for antenna rules, floating wells, and minimum "hot" NWELL width, etc.
Often, electrical rules are specified as topological structures rather than single device/pin checks. Geometrical rules from the layout also are associated with these topologies to ensure proper design function, performance, and yield. Some rules combine both geometrical and electrical checks, and they can differ from one design group to another, exhibiting a high degree of variability.
Electrostatic Discharge Causes Performance and Reliability Concerns
Electrostatic discharge (ESD) and crossing between multiple power domains are two critical areas of concern during verification of circuit performance and reliability, and they involve checking several complex methodology rules. ESD events can have severe harmful and irreversible impacts on devices. Such events usually cause either electrical reliability issues or catastrophic chip failure.
You can overcome ESD problems by using antistatic coatings, shielded materials, and implementing protection circuits within the chip. For example, you could design protection circuits to create a low impedance path that drains ESD current away from design circuitry. However, high probability paths happen between any pairs of chip pads. So, to protect all pairs of pads, n(n-1)/2 protection circuits would be required for n-pad chip just to protect I/O circuitry.
In multiple power domains, other ESD precautions have to be considered. In this case, system integration and IP reuse involves more robust ESD rules to avoid device burnout, which complicates the verification problem and takes it to a much deeper level of constraints. Design hierarchy also comes into play where specific rules are applied on a top cell and/or pad frame but others are applied between blocks that cross multiple power domains. This is by no means a trivial task when performed manually. Automation is necessary to cope with the increasing complexity in advanced technologies.
New Technologies Need to Address Emerging Verification Demands
An EDA solution that helps designers effectively tackle the complex tasks of circuit verification should be user-configurable or programmable so that CAD engineers can customize design checks based on varying requirements. Unique sets of checks could be created that would be totally different in definitions and/or constraints from each other.
Ideally, these checks would be applicable on both netlists and layouts. For example, it would be more efficient and cost-effective if essential electronic design rules could be checked on the schematic rather than waiting for layout implementation. However, some ESD protection circuits are added later on in the cycle directly on the layout even though they were not present in the original schematic design. An automated solution that verifies circuits at both the schematic and layout phase can reduce cost and time to market; and, at the same time, improve yield and design reliability.
A good solution should incorporate circuit topology identification, geometrical measurement and extraction, and user-defined programmable entry to meet the demands of advanced ERC. With every new process node, it becomes more vital to check designs early in the cycle to reduce effort, time, and cost.
Customize Your Electrical Rule Checks for ESD
To address these reliability and performance challenges, a programmable electrical rule checker (PERC) needs to be flexible and customizable using the standard SVRF design rule language for instances, cells, pins, nets, and properties data collection/identification. It should also use standard TCL so that you can more easily define complex circuit topology rules. A PERC tool that uses hierarchical design information can provide quicker turnaround while ensuring high accuracy.
ESD rules are topological in nature (Figure 1) and are tagged to geometrical and electrical constraints. The PERC tool developed at Mentor Graphics addresses major issues such as catching circuits that are not designed to handle certain scenarios from both geometrical and electrical points of view.
1. This example from Mentor Graphics Calibre PERC tool shows a topological ERC that needs a programmable entry for circuit identification. This advanced ERC indicates that serially connected gates cannot be on different supplies or grounds.
(Click this image to view a larger, more detailed version)
Example of a Specified ESD Check
A typical electronic rule check is shown in Figure 2. The requirement is specified by best practices published by the Industry Council on ESD Target Levels . The recommendations define a specific protection circuit formed by groups of devices to sink electrical discharging current away from internal circuit. A customized ERC that checks for the proper ESD protection is shown below the specification. An interactive display shows all the places where the ESD requirement applies and where there are omissions or incorrect implementations. When using this method, you can view either the schematic representation or a layout view to quickly determine the cause of the rule violation and how to fix it.
2. Recommended rule specified by the Industry Council on ESD Target Levels is implemented with the programmable electrical rule checker, and an ESD violation is displayed in the physical layout view.
A New Level of Checking for Multiple Power Domain Crossings
Large system-on-chips that integrate multiple IP blocks, special circuits for low power consumption, and other complexities in the design require keen attention to electrical issues such as multiple power domain crossings. The increasing number of devices or cells per design and deep design hierarchy also have increased the burden on verification. Current EDA tools have not been able to handle this level of complexity associated with specific circuit topologies.
We developed the PERC tool so that it can be customized to handle these challenges. For example, system integration teams could specify all possible violation scenarios that may need to be checked and discovered using TCL programming. (See Figure 3 for an example of a configurable ERC that checks multiple power domains.) These checks could then be more easily performed on the layout or on the schematic for early detection and silicon failure avoidance.
3. An example of a multiple power domain checking rule and ERC configurable code.
Without a doubt, different circuit-verification strategies are required to address reliability and functional yield issues in today's advanced and complex IC designs. Until now, there has been a clear gap in EDA solutions to address the demands of circuit and electrical verification. Complying with electrical rule checks that address reliability issues caused by crossing multiple power domains and potential catastrophic failures from ESD can have large positive effects on yield and performance -- but, at the same time, complying with these new verification rules is difficult and time consuming using conventional approaches. Being able to program electrical rule checks is one more step on the ladder to tackling increasing circuit verification challenges, on both the geometrical and electrical side.
1. White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements, Industry Council on ESD Target Levels, August 2007, http://www.esda.org/.
About the Author
Hazem Hegazy works at Mentor Graphics in Cairo, Egypt. Hazem earned his B.Sc. in Electrical Engineering from Ain-Shams University in Cairo. He also earned his M.Sc. degree from same university specialized in RF VCO circuit design. Currently, Hazem is a Ph.D. candidate, and his thesis work is in substrate noise coupling macro modeling domain of research.