Moore's Law continues to drive chip complexity and performance to new highs, while stressing and periodically "breaking" existing design flows. Fortunately for consumers of electronic design automation (EDA) tools, the same shrinking geometries that make their design problems tougher are also helping to improve the performance of these tools.
But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches, such as hardware description language (HDL) simulation, continue to lose ground. HDL simulation speeds aren't keeping pace with device complexity because many new devices -- 3G cell phones, internet routers and image processors, for example -- require massive verification sequences that would take many years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software to fully verify a new system on chip (SoC) or system design.
Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a causality dilemma: which comes first -- the "final" hardware or the "final" software?
In recent years, a new breed of tools, collectively called virtual prototyping platforms based on a high-level of design abstraction, have been introduced in an attempt to start software validation well ahead of silicon availability. While some may have achieved the scope of jump-starting software development, they only address application programs that do not require an accurate representation of the underling hardware design. They fall short when testing the interaction of the embedded software with hardware, such as firmware, device drivers, operating systems and diagnostics. For this testing, embedded software developers need an accurate model of the hardware to validate their code, while hardware designers need fairly complete software to fully validate their application specific integrated circuit (ASIC) or SoC.
Eventually, both groups need to come together on a common model to verify the complete hardware and the embedded software. For most teams, that first complete model is the actual silicon. See Figure 1.
1. Project progress without emulation.
The problem with waiting for real silicon is that the embedded software can't be fully validated in the context of a complete, accurate system model until late in the design cycle. That increases the probability that problems will be found in the silicon, the software or both, often necessitating additional silicon respins and code revisions. Both have cost and time-to-market implications.
At 90 nanometer (nm), a new mask set costs approximately $1.5 million and may add months of additional delay. What's more, a three-month delay in a fast-moving market can cause a loss of more than 25% of total product lifetime revenue, according to IBS Inc. What's needed to avoid these costs is a hardware-assisted verification approach that can enable hardware/software integration to begin well ahead of first silicon.
Traditional Approaches to Hardware-Assisted Verification
Logic emulation and field programmable gate array (FPGA) prototyping have been around for more than a decade but neither of these approaches provides an optimum solution for hardware/software integration.
Traditional emulation systems offer the large capacity required to emulate complex systems, in addition to hardware debugging features that help designers isolate bugs in their chip design. They are expensive assets and their performance of few hundreds of kilohertz at best is inadequate for embedded software validation. As a result, these systems tend to be relegated exclusively to hardware verification activities, and mostly to large companies with big EDA budgets.
Embedded software teams typically need better performance in excess of a megahertz to run long code sequences, and need more cost-effective systems since they may need multiple copies to support a team of several software developers. FPGA-based rapid prototyping systems are faster than emulators and are less costly. However, for SoC designs that require more than four FPGAs, they are not easy to handle since the design mapping process is virtually manual, error prone and time consuming. Further, they are not well suited to hardware debugging tasks since probe points must be added selectively at compile time. As a result, FPGA prototypes appeal more to software development teams, as long as their designs fit in few FPGAs.
Achieving the Best of Both Worlds
What's needed is a new approach to hardware-assisted verification that combines the strengths of traditional emulation with those of rapid prototyping into a unified solution accessible to both hardware designers and software developers. New hardware-assisted verification solutions are faster and more affordable than traditional emulation systems. They are easier to use, offer higher capacity and better hardware debugging than FPGA prototyping systems. Additionally, they can be integrated with popular HDL simulators and with transaction-level testbenches.
Architected to meet the needs of both hardware and embedded software engineers, they provide hardware and software debugging capabilities to help to debug complex embedded SoC designs.
New hardware-assisted verification solutions' flexibility enables their use throughout the hardware and embedded software development cycle to:
- Verify and debug ASICs/SoCs, intellectual property (IP) cores
- Co-verify hardware and software
- Develop and debug embedded software
With integrated hardware debugging resources and high-execution speeds, these solutions are ideal for verifying and debugging complex hardware blocks, IP cores and full chip designs. Early in the design cycle, these tools can be used as simulation accelerators in co-emulation with HDL simulators and/or C/C++ code. They can be driven by existing HDL testbenches with no modification, and by hardware verification languages (HVL) testbenches, such as Vera and e, albeit with rather limited acceleration factors. In addition, testbenches can be applied externally by the workstation or synthesized and mapped into the emulator. See Figure 2.
1. Project progress with emulation shows time savings.
Later in the design cycle as the pieces of the design come together, the hardware-assisted verification solution can be used to validate the entire system by running the embedded software with either a synthesizable testbench or in co-emulation with C++/System C code on the workstation. They have been architected for fast co-emulation at the transaction level, with operating speeds up to 30 megahertz (MHz). For software debugging, the system's processor can be connected through a JTAG cable or a cabeless JTAG transactor interface to standard embedded software debuggers from ARM, TI and ARC.
The cableless JTAG connection via transactor allows for stopping the clock for tracing hardware bugs in the design hardware. In this way, they can execute software drivers, operating systems or applications at MHz speed, while providing full hardware and software debugging capabilities to both hardware and software engineers on the same design representation. This enables hardware and software development teams to collaborate on the resolution of integration issues in a way that was never possible before.
Hardware-assisted verification can also be used as a dedicated software development platform for embedded software developers, with full access to software development and debugging tools. The embedded software can be downloaded into the design memory via the PCI interface in a fraction of a second and much faster than through the JTAG port. A save and restore capability can be used to skip the OS boot phase and advance directly to the point in the code at which a problem was detected.
EVE has developed breakthrough architecture used in ZeBu (for Zero Bugs), a fast, affordable hardware-assisted verification solution, meeting the needs of both hardware and embedded software engineers. ZeBu incorporates the largest FPGAs available with the highest level of integration and smallest footprint -- all key to the system's capacity, performance and cost-effectiveness. Its compiler automatically handles any design, regardless of size, coding style, clocking scheme or memory structure, making it easy to map even large designs.
Unprecedented device complexity and embedded software content are driving the need for a new hardware-assisted verification approach. What's needed is a tool that combines the strengths of traditional emulation and rapid prototyping into a unified platform for both hardware and embedded software development. This single platform and design representation can satisfy the needs of both these applications, enabling hardware designers and software developers to communicate and collaborate in a way that was never possible before. The net benefit is an ability to accelerate hardware/software integration ahead of first silicon, reduce unnecessary respins and software revisions, shortening the time to market.
About the Author:
Lauro Rizzatti, is General Manager of EVE-USA.