As integrated circuits grow in content and complexity, reaching target yield levels becomes challenging. A product engineer's worst nightmares frequently become reality: sample devices are supposed to be delivered to a demanding customer next week but they don't work on the tester. Yield is still in the single-digit range, and the product needs to be in stores for the holiday season. A large handful of failing devices were carefully selected and sent to failure analysis, but no problem was found.
Although scan diagnosis is an established, automated technique for localizing defects for failure analysis (FA), raising silicon production yield, and assisting first silicon debug, it's often an afterthought and taken for granted. Like a spare tire, it's ignored until you have a flat on an isolated forest road, then you realize that although you thought you were prepared, the spare tire is deflated and the lug wrench is missing.
A spare tire is more useful if it's maintained with sufficient air pressure. Just as well, to get the full benefit from diagnosis, certain requirements have to be understood and considered earlier during the design process, before there's a problem. If ignored, the diagnosis process can be unnecessarily complex or even unfeasible. As a result, the time to finding the root cause of yield loss may be unnecessarily long, failure analysis results may take longer time to produce, and time to production volumes may be delayed.
Scan diagnosis based on logic test
The majority of digital semiconductor designs are tested using design-for-test (DFT) structures such as scan chains. By connecting all sequential elements in a shift register, the task of controlling and observing the circuit is greatly simplified, and the test pattern generation process can be automated using automatic test pattern generation (ATPG) tools. Another flavor of structural test is logic built-in-self-test (BIST) that adds on-chip pattern generation and comparison to the scan design.
Scan diagnosis leverages existing DFT structures and production test patterns to determine why a digital semiconductor device fails during manufacturing test and where the defect causing the failure is located. This process leverages the design description (typically a gate level and layout representation), test patterns used to detect the failure, and the failure data from the tester. Scan diagnosis is based on ATPG technology and can therefore only be used to diagnose failures occurring during the execution of ATPG pattern or BIST, not functional patterns.
The following illustrates the steps a diagnosis tool goes through to analyze the actual response observed on the tester and determine which fault(s) might have caused this failure (Figure 1):
1. Trace back from each failing scan cell and identify which suspects (fault location and mechanism, such as "stuck-at 0") could have caused the failures.
2. Simulate the effect of each suspected fault to determine if the simulated effect matches the actual response. Eliminate the suspects that failed in the simulation, but passed in silicon.
3. Rank suspects to identify which faults are most likely to have caused the failure.
Click on image to enlarge.
Figure 1: Scan diagnosis algorithm example where the tester observed unexpected results in two scan cells.