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High-level synthesis, verification and language

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Matthieu Wipliez
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re: High-level synthesis, verification and language
Matthieu Wipliez   7/9/2014 4:02:17 PM
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Interesting post, and indeed it makes much more sense to use SystemC than C, because to be synthesized into anything useful, you will have to rewrite a lot of code to the point that it won't really bear much resemblance to the original source. That said, writing SystemC code to design hardware is a PITA, and if you want to write something synthesizable by all vendors, you basically have to resort to RTL-like SystemC, which is about as ugly as it seems. Also, technically SystemC is not even a language, rather a huge pile of templates on top of C++ (which in itself is already pretty complex).

Why don't you use a modern language? A language that has first-class support for task-level parallelism and inter-task communications, that is a clean subset of the C syntax, without anything that makes no sense on hardware (like pointers and dynamic memory allocation). Oh and the compiler is open-source so you don't need to worry about us being acquired (like Forte and Synfora). Learn more at synflow.com and come discuss on our forum. Cheers!

Andyh
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re: High-level synthesis, verification and language
Andyh   3/3/2010 7:31:40 PM
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John, I agree with your position that verification of the architectural model should take place at a high level, not at RTL. Getting the verification flow right is where the biggest gains come from in moving to ESL design. However, Synfora offers this flow while maintaining design entry at the untimed C/C++ level. At this level, timing and parallelization is left to the compiler making the code easier to create and debug. In order to verify the architectural model at a high level PICO C Synthesis generates both bit accurate and thread accurate SystemC models to enable the superior verification flow that you outline. Readers can learn more at www.synfora.com Andy Haines

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