The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.
High-level design has many advantages over the more commonplace design flow which begins with RTL code. Among the most compelling advantages is the improved verification efficiency which a higher level of abstraction offers. It is apparent to the point of being self-evident that when the source code of a design is created, there will be fewer errors if the source is at a higher abstraction level than if it is at a lower level. However, there is still a process required to verify the transformations which are applied to the design description as it proceeds through the design flow from creation to final realization.
Figure 1 shows the initial steps in the High-level Design (HLD) flow, without any of the verification steps shown. There is more than one way to place the verification steps in this flow, and the choice of where they go is heavily influenced by the high-level design language that is the input to the RTL Creation, or High-level Synthesis (HLS) step.
| Figure 1. High-level design flow|
Figure 2a shows how the verification steps fit if the HLD input language is "Plain old C"( PoC) - ANSI-C or C/C++ - and figure 2b shows where the verification steps fit if the HLD input language is SystemC. There is an additional verification step in the SystemC flow, which is labelled a validation step. For our purposes, verification means demonstrating that the design functions correctly. Validation means demonstrating that the design has the same functionality as a previous version of the design.
| Figure 2a Verification in a PoC high-level SystemC design flow |
| Figure 2b Verification in a high-level design flow|