Power Delivery Network (PDN) has traditionally been a disjointed design problem with chip, package and board engineers doing their part of the design with margins assumed for the other parts. As 45nm designs become more common and the first set of 32/28nm tape-outs start to happen, certain trends are becoming quite clear:
a) A holistic approach to PDN design, analysis and verification considering the simultaneous interplay of chip, package and board layouts is becoming a standard design methodology.
b) Static (DC) voltage drop analysis is limited mostly to ensuring gross connectivity and for electromigration verification and checks.BR>
c) Detailed die level time-domain analyses considering all the different power domains, voltage islands, power gating circuits, package and board inductors and resistors, on- and off-die decoupling capacitors is a sign-off requirement.
d) Multiple analyses covering different operations of the die: functional mode, clock gating transitions, power-up, power-down, scan mode (LBIST, ATPG, MBIST) are now required as part of the time-domain simulation checks. The realization is that given the complexity of the circuits with the likelihood of failure quite high from Dynamic Voltage Drop (DvD) induced failures, any one check cannot uncover all the potential problems in the design.
e) Package and board level analyses (frequency and time-domain) increasingly rely on accurate die models created using the Chip Power Model (CPM) technology .
Let us consider the impact of decoupling capacitance on the design of power delivery network for advanced designs. If we were to take a decap cell, say DECAP32, and look at its effective intrinsic capacitance (ESC) and resistance in various technology nodes (130, 90, 65 and 45nms), we see that the intrinsic capacitance is going down significantly while the effective series resistance (ESR) is going up considerably. Figure 1 illustrates the trend.
Figure 1: Change in decap intrinsic capacitance and resistance for different technology nodes.
Click on image to enlarge.
From this chart, we see that in 45nm, the capacitance is about 9 percent of what it was for the same cell in 130nm while the ESR is about 6X higher. So the effectiveness of the decap cells in providing charge is decreasing considerably. That coupled with the overall higher resistance seen in the on-die power grid network makes the proper placement of the decap cells quite important to ensure that they are effectively used. A robust time-domain analysis methodology covering different operating scenarios of the die is thus required to determine the design, placement and count of the intentional decoupling capacitance on the die. In this analysis, the impact of the package and board must be considered along with full die-level detail. The package and board can be represented through distributed RLCK or S-parameter models. Additionally the time domain analysis must be done for different scenarios for multiple clock periods with time step resolution of at most 10ps or less for 45nm and more advanced designs.
At the same time, the package and board design teams need to include an accurate model of the die (or dies depending on the package) to ensure that they model the impact of the die capacitances in their frequency domain analyses of their package and board designs.