Energy conservation has become a key social objective in all aspects of our lives. Due to the pervasiveness of electronics and computing, the processor industry accounts for an ever increasing share of world power consumption; be it for processors used in personal computers, domestic and industrial appliances, in massive server farms, or even in the growing number of mobile smart-phone devices.
For the engineers and designers creating these electronics, delivering a high-performance design, while keeping energy conservation in mind, remains a delicate balance. Fundamental advances at the silicon design level, however, have led to significant improvements in power efficiency for many of these electronics. To that effect in the last few years much of the attention of the industry has been focused on multicore architectures. While this architecture shift has certainly helped address some power concerns, a lesser known processor design methodology holds the promises for even more significant power savings. This is the adoption of self-clocking processing cores.
The power/performance/cost trade-off
A decade ago, migrating to new and smaller geometry process nodes was an exciting proposition: faster clock speeds, twice as many chips per wafer and of course much lower power consumption. As transistor geometries have scaled towards the most fundamental atomic dimensions, it has become increasingly difficult to get improvements in the three product fundamentals of performance, cost and power. Instead of obtaining improvements in all three, design teams have had to optimize for two of the three fundamentals; either optimize for power and cost with tradeoffs in performance, or optimize for performance gains and tradeoff higher power dissipation with marginal cost improvements. This has had to be done against a backdrop of much higher development costs and of course, increased design complexity and risk. These trends have in turn made the return on investment evaluations for complex SoCs much harder.
Until recently, the major performance gains in microprocessor evolution were done by using smaller and faster transistors made available in each technology node to increase clock frequency. Architectural gains and increased data path widths further improved performance while reduction in core operating voltages improved power consumption. At the 90nm technology node, transistor leakage current became a major challenge. Smaller transistors with lower threshold voltages could reduce chip area and increase performance, but brought a high cost in increased leakage current. Designers now face a difficult choice between increasing clock frequency to improve performance and paying a large penalty in power consumption, or reducing power with little gain in the performance per gate of the design and using more gates (silicon) for performance gains.
The key strategy adopted by the industry has been the use of many slower processors within a single device and hence the well-known shift to multicore architectures. Reducing the clock frequency makes each processor more power efficient, and therefore greener.
Multicore processors have become increasingly popular, due largely to their ability to reduce power consumption and offer increases in system performance. Clearly two processors can do more useful work than one and use less power than simply clocking a single processor at twice the clock frequency. This architecture change allows greater power efficiency but causes two major side effects: reduced silicon efficiency and higher system complexity.
Since the multicore architecture requires multiple copies of the same core, it directly trades area to increase system performance. Any reductions in die size due to smaller transistor geometries are lost on the need to implement multiple cores.
Challenges with traditional processor design
As geometries scale below 40nm, leakage current continues to be an issue. Another added challenge is managing on-chip process variations. Variation in two key semiconductor process parameters, transistor threshold voltage and transistor effective length can have a substantial impact on the performance and power consumption of a design. As these variations in the manufacturing process increase, designers of SoCs at these nodes have to be much more conservative and slow down the frequency of operation in order to guarantee that the design will not only meet its performance specifications, but will also be manufacturable.
Another issue that has been well publicized for semiconductor evolution is heat generation and dissipation. Power dissipation is proportional to capacitance, and voltage squared. Prior to 90nm, as technology shrank the switching voltage was also reduced yielding a reduction in power. As the operational voltage is now close to the threshold voltage of a single transistor, it is not possible to get the same reductions in power dissipation to offset the shrinking area of the chip. As semiconductor process technology puts more gates in a given area without this commensurate, decrease in power consumed by the gates the heat generated for a given area increases. With a limited power dissipation capability of the package and heat sink, migration to smaller geometries with increased clock frequencies rapidly exceeds the ability to remove the heat thus limiting the performance achievable by a design.