When a verification environment is needed for a new design, or for a design revision with significant changes, it is important to objectively look at the shortcomings of the existing verification environment and expected productivity gain with the new methodology and determine the best solution.
In most cases, we need to find an optimum balance between re-usability of our legacy Verilog environment and the resource utilization along with limited timelines in adopting the new methodology. This can be accomplished by reusing the knowledge/legacy code from an earlier project along with an upgrade to a new methodology provided with the verification language that is SystemVerilog.
There are already a few verification methodologies available such as VMM and OVM which help in building a robust verification flow. But keeping in our limited resources and stringent timelines, we may have to focus on implementing a simpler flow based on Constraint Random Techniques (CRT), which helps in generating the interested test scenarios automatically. This all is performed and implemented with in-built features available with SystemVerilog.
This document demonstrates the introduction of Constraint Random Verification with SystemVerilog while re-using the legacy Verilog verification environment (keeping what we knew best).
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