Radio Frequency (RF) and wireless applications are made up of a number of analog and digital building blocks, and a combination of each one of them can be present on a system-on-chip (SoC), or system-in-package (SiP) design.
Many of the current wireless systems rely exclusively on digital modulation as opposed to older-generation systems which were based on analog modulation. Digital modulation has prevailed as it offers increased channel capacity, improved transmission-quality, secure communication and the ability to provide other value-added services.
At the same time, RF front-ends are still predominantly analog functions with power amplifiers (PAs), low-noise amplifiers (LNAs), mixers, up/down converters, and voltage-controlled oscillators (VCOs). However, the Intermediate Frequency (IF) sections are moving from analog to digital functions using direct digitization with high-speed pipeline data converters and DSP-based baseband modulation synthesis and analysis. It is these functions that form the basis of the Software Defined Radio (SDR) and its multimode and multi-band capability.
Digitized Wireless Tests
There are a number of critical test parameters for wireless systems, most of which are associated with the analog over-air transmit and receive signals. Examples include scatter parameters, harmonics, inter-modulation distortion, spurious emissions, random and deterministic noise, signal isolation and dynamic range.
Tests associated with digitally modulated signals include spectral re-growth, a term that defines inter-modulation distortion. The in-band effects of spectral re-growth cause errors in the symbol vectors that lead to intersymbol interference (ISI) and a lower Bit Error Rate (BER) within the system. The figure of merit that characterizes this effect is referred to as Error Vector Magnitude (EVM). The out-of-band spectral re-growth leads to Adjacent Channel Power (ACP) leakage, which causes interference to other users within the network.
In typical modern digital receivers, the output of the IF stage is directly digitized, and all subsequent signal processing is performed digitally. To establish receiver goodness, EVM measurements must consider both the analog and digital filter elements using the In-phase Quadrature modulated signals (IQ). IQ measurements accurately test the effects of these filters, as well as error sources such as ADC aperture uncertainty and down converter process noise. The characteristics of these filters are critical in eliminating inter-symbol interference and achieving a high signal to noise ratio.
Adjacent Channel Power Ratio (ACPR) is the power ratio of the power in the two adjacent channels to the power in the main channel. Channels in most digital wireless systems are arranged to be overlapping, so that some power intended for the main channel inherently appears in the adjacent channels, Figure 1. The overlap is a compromise between the finite roll-off of the filters and the need to maximize spectral efficiency.
Nonlinear amplification of the filtered spectrum will generate intermodulation distortion (IMD), leading to regeneration in the adjacent channels of the filtered spectrum. The degree of spectrum regeneration is characterized by the ACPR, which is the limiting factor in achieving high efficiency amplification. Therefore, ACPR is the figure-of-merit for linearity characterization for digital
Test Interface challenges
For many RF and wireless measurements, the electrical interface between the device being tested and the test equipment must be pristine. Many of the signals require matched and stable impedances, low noise floor, a high degree of isolation, excellent grounding, and RFI and EMI screening. Many device signals are carrier related ratios, such as in-band spurious emissions (-80dBc), intermodulation distortion (-70dBc) and Adjacent/Alternate Channel Power Ratio (-80dBc). Other very-sensitive measurements include noise figure at just a few dB above reference (-174dBc/Hz) and local oscillator isolation (-80 to -100dBm). All require an accurately controlled interface that minimizes any signal derogation.
Testing these devices to the level of performance required, and at an acceptable cost, is one of the semiconductor industries' biggest challenges. High-performance test systems are custom tailored to the device being tested via what is known as a loadboard, or interface board; this board houses interface conditioning and buffering circuitry between the Device Under Test (DUT) and the test instrumentation, and it houses some of the most critical circuitry for maintaining measurement accuracy.
Another very critical link is the test socket; the test socket is the interface between the device being tested and the loadboard. Under ideal test conditions, the DUT would be electrically soldered directly onto the loadboard, but this is impractical in a test environment where many devices have to be tested, and in many cases in just a few hundred milliseconds. In this case a socket has to be used.
Test socket challenges
The test socket, Figure 2, must deal not only with the electrical characteristics of all the different interface connections required, but it also has to deal with the mechanical abuse of thousands of device packages being inserted and removed by an automated handling system.
Figure 2: The test socket must provide electrical and mechanical integrity and repeatability for many cycles
There are two main users involved with test socket selection. The first is the test engineering or product engineer who is primarily interested in establishing the ultimate electrical performance of the semiconductor device. He or she is looking to accurately verify the electrical specifications in order to establish the highest selling value for the product; therefore, electrical performance is of prime importance.
The second user is the production engineer; and while he or she has to verify the electrical performance specified by the product engineer in a production environment; the mechanical consistency, reliability, dependability and the lowest cost over a large number of device insertions is the prime concern; especially as it has to be done in an automated handling environment that can be mechanically very harsh on any device interface. These issues have to be considered when designing a test socket for the high performance interface applications discussed above.
Electrical and Mechanical Challenges
The test socket has to consider many different electrical specifications both at DC and at high frequencies. These parameters include overall electrical length, contact resistance, inductance and capacitance, all of which effect operating bandwidth. For high-frequency applications, the socket becomes part of an overall transmission line and therefore scattering parameters (S- parameters) for insertion and return loss have to be considered. Crosstalk between contacts must also be addressed.
A socket also has to consider all the mechanical issues associated with device presentation and alignment. There are a number of interconnect pitch- and profile-dimension tolerances, package tolerances and handling-systems alignment and presentation tolerances. All of these tolerances interact with each other in multiple combinations, and must be considered and accounted for in the overall socket mechanical design.
To overcome these obstacles, a socket has to provide consistent and repeatable electrical performance over a large number of device insertions, and accommodate the multiple mechanical variances. Only a socket which uses a highly accurate and adaptive design parameters can achieve this.
Lead-free package interconnects
An area that has aggravated the situation, and exasperated users, in both electrical and mechanical aspects of socket technology has been the introduction of lead-free package interconnects; these lead-free devices have proven to reduce throughput efficiency and increase the overall cost of test.
Lead-free materials come with surface oxides that cause increased and highly variable contact resistance based on residual oxide debris; this debris has to be penetrated to achieve a good electrical connection. Other mechanical factors that effect overall interconnect electrical performance include socket-contact plating, device-ball alloy amalgamation, effective electrical contact-surface area, and the overall mechanical force required to achieve and maintain acceptable electrical performance.
To minimize the effects of device-interconnect surface oxides, test-socket contact-oxide build-up, and amalgamation between the socket contact and the device-ball material, a penetration and self-cleaning mechanical action is essential. Applying the right amount of force in conjunction with the other contact-pin dynamics is also essential to generate repeatable, low-resistance connections on all contacts and for all device insertions.
A superior solution must provide the necessary electrical and mechanical performance required to sustain the value economics in a production environment. "Value," in this case, means improving test throughput and cost efficiency for high-performance lead-free devices, which is dependent on three major factors: test-cell availability, test throughput, and first-pass yield quality.
Test cell availability is when the cell is testing parts while test-cell changeover and set-up, contact cleaning and rebuilding render the cell down and unavailable. Contactors which require less-frequent cleaning, or replacement and can be set-up, cleaned and rebuilt in a very short time add to test-cell productivity and availability.
Test throughput is represented by the number of units tested per hour via an optimized test program and minimized handling time. Both test-program wait states for electrical and mechanical settling, and guard-band extensions to accommodate electrical variances in the interface, impact overall test productivity.
Yield quality is a measure of first-time yield success and its true throughput value. The need to retest parts based on inconsistent contact-continuity impacts throughput and yield expectancy. Contactors with short cleaning and rebuild cycles, based on the limitations discussed, impact first-time yield, downtime and cost.
About the author
Paul Scrivens is a Senior Product Manager at Johnstech International Corp., responsible for its area array products. Paul has spent the past twenty-five years in the semiconductor test industry, specializing in the area of mixed-signal design and test, holding a number of senior business and marketing positions. Before joining the ATE industry, Paul was a mixed-signal system and circuit design engineer based in the UK.