Programmable integer-N phase lock loop (PLL) ICs are primarily used to reduce the overall system cost and board space by replacing multiple oscillators, crystals, and other timing ICs. These programmable devices can generate one or several high-performance output frequencies from a low-cost, low-frequency input (crystal or reference clock).
A programmable integer-N PLL IC can include one or several such PLLs. In principle, all elements of a PLL can be programmable. In practice, the programmability is usually limited to the R, N, and P counters and, sometimes, the charge-pump current. The equation which defines output frequency shows that the specified output frequency is approximated by selecting the values of N, P, and R.
This article looks at the design trade-offs related to R, N, and P counter selection for optimum performance. These factors limit the useable values of N, P, and R, making the approximation of the specified output frequency by the PLL more difficult.
To read the article, click here.
About the author
Boris Drakhlis is a product and characterization Engineer at PhaseLink Corporation, Fremont, CA, http://www.phaselink.com. He received his engineering degree from Leningrad Polytechnic Institute and has worked as a development engineer in the areas of quartz crystals, oscillator modules, and clock ICs for the last 30 years.