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Design considerations when using programmable integer-N PLL ICs

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biff44
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re: Design considerations when using programmable integer-N PLL ICs
biff44   7/21/2009 11:48:36 AM
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The paper is a little bit confusing. The assumption in the paper, which is not that clearly stated, is that you are using a clock multiplier type PLL IC, where you do not have access to the loop filter design. You can only change the divider ratios in the chip. If that is your constraint, then some of the comments start to make more sense. Increasing the divisor N will, in that case, lower the open loop gain, and that makes the PLL bandwidth smaller. Since the PLL bandwidth is ~related to its frequency pull-in range, then yes, at some point you are not going to be able to track frequency steps. If you have that sort of unique application, then you would not want to use one of these "canned" IC's, and instead would want to use a regular PLL chip with an independent loop filter. That way you can dial up any R or N value you want, and just use an OP amp to add more loop filter gain to broaden the PLL bandwidth. Also, that allows you to design the loop filter specifics, with a control loop zero in the right place, to keep the new PLL design stable too. Rich Maguffin Microwave LLC

Tom VanCourt
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re: Design considerations when using programmable integer-N PLL ICs
Tom VanCourt   7/15/2009 4:16:10 PM
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I'd be interested in seeing a discussion of how R and N affect the PLL's ability to track fast changes in input frequency. Since the phase comparator can operate on only 1/N of the VCO edges and 1/R of the input edges, one application I saw had trouble tracking when those values got large. Unmodulated input worked fine for large R and N, small R and N worked fine for modulated input, but tracking failed for large R or N (I forget which) on the modulated signal.

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